[coreboot] r916 - in coreboot-v3/arch/x86: . i586 via

svn at coreboot.org svn at coreboot.org
Sat Oct 11 03:01:07 CEST 2008


Author: hailfinger
Date: 2008-10-11 03:01:07 +0200 (Sat, 11 Oct 2008)
New Revision: 916

Modified:
   coreboot-v3/arch/x86/Kconfig
   coreboot-v3/arch/x86/i586/stage0.S
   coreboot-v3/arch/x86/via/stage0.S
Log:
Whitespace fixes, readability improvements.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig	2008-10-11 00:07:36 UTC (rev 915)
+++ coreboot-v3/arch/x86/Kconfig	2008-10-11 01:01:07 UTC (rev 916)
@@ -64,7 +64,6 @@
 	  arch/x86/Makefile for more hints on possible values.
 	  It is usually set in mainboard/*/Kconfig.
 
-
 config CONFIG_HPET
 	boolean
 	depends CPU_AMD_K8

Modified: coreboot-v3/arch/x86/i586/stage0.S
===================================================================
--- coreboot-v3/arch/x86/i586/stage0.S	2008-10-11 00:07:36 UTC (rev 915)
+++ coreboot-v3/arch/x86/i586/stage0.S	2008-10-11 01:01:07 UTC (rev 916)
@@ -69,21 +69,15 @@
 
 .align 4
 
-
-
-/* We will use 4Kbytes only for cache as ram. This is
- * enough to fit in our stack.
- *
- * disable HyperThreading is done by eswar
+/* disable HyperThreading is done by eswar
  * the other is very similar to the AMD CAR, except remove amd specific msr
  */
 
 #define CacheSize CONFIG_CARSIZE
-
 #define CacheBase CONFIG_CARBASE
 
 #define ASSEMBLY
-#include "mtrr.h"
+#include <mtrr.h>
 
 	/* Save the BIST result */
 	movl    %eax, %ebp
@@ -175,6 +169,7 @@
 	/* Clear all MTRRs */
 	xorl	%edx, %edx
 	movl	$fixed_mtrr_msr, %esi
+
 clear_fixed_var_mtrr:
 	lodsl	(%esi), %eax
 	testl	%eax, %eax
@@ -331,8 +326,7 @@
 
 lout:
 	/* Store zero for the pointer to the global variables. */
-	movl    $0, %eax
-	pushl   %eax
+	pushl   $0
 
 	/* Restore the BIST result. */
 	movl	%ebp, %eax

Modified: coreboot-v3/arch/x86/via/stage0.S
===================================================================
--- coreboot-v3/arch/x86/via/stage0.S	2008-10-11 00:07:36 UTC (rev 915)
+++ coreboot-v3/arch/x86/via/stage0.S	2008-10-11 01:01:07 UTC (rev 916)
@@ -1,6 +1,6 @@
-/* 
+/*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
  * Copyright (C) 2005 Eswar Nallusamy, LANL
  * Copyright (C) 2005 Tyan
@@ -10,16 +10,16 @@
  * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
  * Copyright (C) 2008 VIA Technologies, Inc.
  * (Written by Jason Zhao <jasonzhao at viatech.com.cn> for VIA)
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA





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