[coreboot] AMD Serengeti Cheetah devices

[ron minnich]

OK, here you go, I cleaned the dts up a bit more and get:
<8>dynamic PCI: 00:00.0(PCI: 00:06.0): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.0(PCI: 00:07.0): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.1(PCI: 00:07.1): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.2(PCI: 00:07.2): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.3(PCI: 00:07.3): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.5(PCI: 00:07.5): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.6(PCI: 00:07.6): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:07.7(PCI: 00:07.7): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:0a.1(PCI: 00:0a.1): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 00:0b.0(PCI: 00:0b.0): enabled 1 have_resources 1 initialized 0
<8>dynamic PCI: 00:0b.1(PCI: 00:0b.1): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:00.0(PCI: 01:00.0): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:00.1(PCI: 01:00.1): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:00.2(PCI: 01:00.2): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:01.0(PCI: 01:01.0): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:04.0(PCI: 01:04.0): enabled 1 have_resources 1 initialized 1
<8>dynamic PCI: 01:05.0(PCI: 01:05.0): enabled 1 have_resources 1 initialized 1

which exactly matches simnow.


On Thu, Oct 9, 2008 at 6:41 AM, Peter Stuge <peter at stuge.se> wrote:
>
> Ok, enable USB.

I just added it in to dts and it finds both usb and usb2.


> Why treat nic and ide differently here? And what about that USB? Is
> it automatically added - and ide+nic needs to be explicitly listed?

I now list them all.

> +++ arch/x86/Makefile (working copy)
> -                     pci_ops_conf1.c resourcemap.c
> +                     pci_ops_conf1.c

> Just cleanup? Isn't resourcemap needed because of the change or was
> it never needed?

It turns out many newer targets will not need this done in stage0, and
space is limited. So mainboards that need it in stage0 will have to
list it.

Committed revision 910.

And etherboot is working :-)

ron