[coreboot] Intel i855pm northbridge

Vincent Legoll vincent.legoll at gmail.com
Sun Oct 5 01:27:01 CEST 2008


I'm trying to understand i855pm code, and reading reset_test.c, I see:
#define MCH_DRC 0x70

whereas the 252613.pdf I downloaded from intel web site, at:
"Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet"
revision 003, page 71, has the following:

3.7.20. DRC – DRAM Controller Mode Register – Device #0
Offset:             7C-7Fh
Default:            1000_0001h
Access:             Read/Write
Size:               32 bits

So what am I missing in the 0x70h versus 0x7Ch difference ?

Could someone please gently enlighten me ?

Vincent Legoll

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