[coreboot] r879 - in coreboot-v3: . arch/x86 device lib mainboard mainboard/amd mainboard/amp mainboard/gigabyte mainboard/pcengines
svn at coreboot.org
svn at coreboot.org
Wed Oct 1 20:29:22 CEST 2008
Author: uwe
Date: 2008-10-01 20:29:22 +0200 (Wed, 01 Oct 2008)
New Revision: 879
Modified:
coreboot-v3/Kconfig
coreboot-v3/arch/x86/Kconfig
coreboot-v3/device/Kconfig
coreboot-v3/lib/Kconfig
coreboot-v3/lib/console.c
coreboot-v3/mainboard/Kconfig
coreboot-v3/mainboard/amd/Kconfig
coreboot-v3/mainboard/amp/Kconfig
coreboot-v3/mainboard/gigabyte/Kconfig
coreboot-v3/mainboard/pcengines/Kconfig
Log:
Minor fixes and improvements for v3, mostly for Kconfig files (trivial).
- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -64,7 +64,7 @@
bool "Enable whole-program optimizations (DANGEROUS)"
depends EXPERT && EXPERIMENTAL
help
- Enable gcc -fwhole-program -combine for select code.
+ Enable 'gcc -fwhole-program -combine' for select code.
Needs lots of annotation in stage1 and stage2.
Works for initram only.
This increases compile time (no parallel compilation possible
@@ -111,8 +111,6 @@
config SUPERIO_ITE_IT8716F
boolean
-# Source all northbridge/southbridge/superio Kconfig files:
-
menu "Payload"
config PAYLOAD_ELF_LOADER
@@ -122,8 +120,8 @@
This option allows an unparsed ELF paylaod to be added and loaded.
choice
- prompt "Payload type"
- default PAYLOAD_NONE
+ prompt "Payload type"
+ default PAYLOAD_NONE
config PAYLOAD_ELF
bool "An ELF executable payload file"
Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/arch/x86/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -60,62 +60,62 @@
boolean
depends CPU_AMD_K8
help
- Whether to configure a High Precision Event Timer. Note that HPETs are
- known to be bug-prone.
+ Whether to configure a High Precision Event Timer (HPET). Note that
+ HPETs are known to be bug-prone.
config K8_REV_F_SUPPORT
hex
default 0 if CPU_AMD_K8
help
- Whether to include rev F support
+ Whether to include rev F support.
config K8_SCAN_PCI_BUS
hex
default 0 if CPU_AMD_K8
help
- Whether to scan the PCI bus in stage1
+ Whether to scan the PCI bus in stage1.
config K8_ALLOCATE_IO_RANGE
hex
default 0 if CPU_AMD_K8
help
- Whether to allocate IO space in stage1
-
+ Whether to allocate I/O space in stage1.
+
config K8_ALLOCATE_MMIO_RANGE
hex
default 0 if CPU_AMD_K8
help
- Whether to allocate MMIO space in stage1.
- Comment from code:
- Do we need allocate MMIO? Currently we direct
- last 64M to southbridge link (sblink) only,
- We can not lose access to last 4M range to ROM.
-
+ Whether to allocate MMIO space in stage1.
+
+ Comment from code: Do we need allocate MMIO? Currently we direct
+ last 64M to southbridge link (sblink) only. We can not lose access
+ to last 4M range to ROM.
+
config LOGICAL_CPUS
hex
depends CPU_AMD_K8
default 1
help
- How many logical CPUs there are. Fix me.
+ How many logical CPUs there are. FIXME.
config MAX_PHYSICAL_CPUS
hex
depends CPU_AMD_K8
default 1
help
- Max number of physical CPUs (sockets)
+ Maximum number of physical CPUs (sockets).
config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
hex
default 0 if CPU_AMD_K8
help
- Config with 4 CPUs even if more are installed
+ Config with 4 CPUs even if more are installed.
config CROSS_BAR_47_56
hex
default 0 if CPU_AMD_K8
help
- Configure for the type of crossbar on the mainboard.
+ Configure for the type of crossbar on the mainboard.
config OPTION_TABLE
boolean
@@ -128,14 +128,14 @@
boolean
help
This option is used to determine whether the mainboard has
- a PIRQ table, which is the old way to set up interrupt routing.
+ a PIRQ table, which is the old way to set up interrupt routing.
It is usually set in mainboard/*/Kconfig.
config ACPI_TABLE
boolean
help
This option is used to determine whether the mainboard has
- an ACPI table.
+ an ACPI table.
It is usually set in mainboard/*/Kconfig.
config SMP
@@ -143,9 +143,8 @@
depends CPU_I586 || CPU_AMD_K8
default 0
help
- This option is used to enable certain functions to make
- coreboot work correctly on symmetric multi processor
- systems.
+ This option is used to enable certain functions to make coreboot
+ work correctly on symmetric multi processor systems.
It is usually set in mainboard/*/Kconfig.
config IOAPIC
@@ -153,7 +152,7 @@
depends ARCH_X86 && CPU_AMD_K8
default 0
help
- If you want to configure an IOAPIC, set this.
+ If you want to configure an IOAPIC, set this.
config CARBASE
hex
@@ -177,36 +176,37 @@
default 0x1000 if CPU_AMD_GEODELX
default 0x2000 if CPU_AMD_K8
help
- This option sets the top of the memory area, in KiB,
+ This option sets the top of the memory area, in KiB,
used for coreboot.
config K8_HT_FREQ_1G_SUPPORT
hex
default 1 if CPU_AMD_K8
help
- 1 Ghz. support. Opteron E0 or later can support
- 1G HT, but still depends on the mainboard
+ 1 GHz support. Opteron E0 or later can support 1G HT,
+ but still depends on the mainboard.
config HT_FREQ_800MHZ
hex
default 1 if CPU_AMD_K8
help
- Can we run HT at 800 Mhz
+ Can we run HT at 800 MHz.
config USBDEBUG_DIRECT
boolean
depends SOUTHBRIDGE_NVIDIA_MCP55
default 0
help
- Determines if we enable USB Direct debugging. If you don't have a dongle,
- this is probably of no value to you.
+ Determines if we enable USB Direct debugging. If you don't have
+ a dongle, this is probably of no value to you.
config APIC_ID_OFFSET
hex "APIC ID offset"
default 0x10
depends IOAPIC
help
- This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting.
+ This is entirely mainboard dependent. 0x10 is a *typical* setting
+ but not always a good setting.
menu "Debugging"
@@ -214,6 +214,6 @@
bool "Test CAR area"
default n
help
- Test the CAR area after it has been set up.
+ Test the CAR area after it has been set up.
endmenu
Modified: coreboot-v3/device/Kconfig
===================================================================
--- coreboot-v3/device/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/device/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -36,7 +36,6 @@
execute PCI option ROMs natively (32bit x86 system required),
in an emulator (x86emu), or ignore option ROM execution.
-
config PCI_OPTION_ROM_RUN_X86EMU
bool "x86emu"
select PCI_OPTION_ROM_RUN
@@ -47,7 +46,6 @@
x86emu is slow, big and safe. All 16bit x86 code is executed
in an encapsulated environment where it can not break out.
-
config PCI_OPTION_ROM_RUN_VM86
bool "vm86"
select PCI_OPTION_ROM_RUN
@@ -64,7 +62,6 @@
bool "Disabled"
help
Do not execute PCI option ROMs at all.
-
If you choose this option, VGA plugin cards will not be initialized.
endchoice
@@ -74,7 +71,7 @@
bool "Initialize all VGA cards"
depends PCI_OPTION_ROM_RUN
help
- If you enable this option, all VGA cards will be initialized
+ If you enable this option, all VGA cards will be initialized.
If you disable this option, only the first VGA card will be
initialized.
@@ -82,7 +79,7 @@
bool "Initialize onboard VGA first"
depends PCI_OPTION_ROM_RUN
help
- Initialize onboard VGA chips before any plugin VGA cards
+ Initialize onboard VGA chips before any plugin VGA cards
are initialized.
endmenu
@@ -99,17 +96,17 @@
bool "64 bit prefetchable memory addresses"
depends CPU_AMD_K8
help
- Enable support for 64-bit prefetchable memory addresses in PCI.
+ Enable support for 64-bit prefetchable memory addresses in PCI.
config HW_MEM_HOLE_SIZEK
hex "HW memory hole size in KB"
depends CPU_AMD_K8
default 0x1000
help
- Some chipsets support setting up a "hole" at the top of memory. It is essentially
- a hole torn in the physical address space so that you can fit non-memory resources
- (e.g. flash) at the top of the 4G address space. Given that this only happens on machines
- with lots of memory, the default 4 MB is a very reasonable value.
-
+ Some chipsets support setting up a "hole" at the top of memory.
+ It is essentially a hole torn in the physical address space so that
+ you can fit non-memory resources (e.g. flash) at the top of the 4G
+ address space. Given that this only happens on machines with lots
+ of memory, the default 4 MB is a very reasonable value.
endmenu
Modified: coreboot-v3/lib/Kconfig
===================================================================
--- coreboot-v3/lib/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/lib/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -200,15 +200,21 @@
Debug Port capability. Controllers which are known to work:
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
- * 10de:0088 NVIDIA MCP2A
- * 10de:005b NVIDIA CK804
- * 10de:036d NVIDIA MCP55
+ * 8086:24cd Intel ICH4/ICH4-M
* 8086:24dd Intel ICH5
* 8086:265c Intel ICH6
* 8086:268c Intel 631xESB/632xESB/3100
* 8086:27cc Intel ICH7
* 8086:2836 Intel ICH8
* 8086:283a Intel ICH8
+ * 8086:293a Intel ICH9
+ * 10de:0088 NVIDIA MCP2A
+ * 10de:005b NVIDIA CK804
+ * 10de:026e NVIDIA MCP51
+ * 10de:036d NVIDIA MCP55
+ * 10de:03f2 NVIDIA MCP61
+ * 1002:4386 ATI/AMD SB600
+ * 1106:3104 VIA VX800
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
@@ -216,12 +222,12 @@
depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
config CONSOLE_PREFIX
- bool "Prefix all console output with '(LB)'"
+ bool "Prefix all console output with '(CB)'"
depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
default n
help
When you enable this option, coreboot will prefix each line of
- console output with '(LB)'.
+ console output with '(CB)'.
config CONSOLE_BUFFER
boolean "Console memory buffer support"
Modified: coreboot-v3/lib/console.c
===================================================================
--- coreboot-v3/lib/console.c 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/lib/console.c 2008-10-01 18:29:22 UTC (rev 879)
@@ -116,7 +116,7 @@
#ifdef CONFIG_CONSOLE_PREFIX
uart8250_tx_byte(TTYSx_BASE, '\n');
uart8250_tx_byte(TTYSx_BASE, '(');
- uart8250_tx_byte(TTYSx_BASE, 'L');
+ uart8250_tx_byte(TTYSx_BASE, 'C');
uart8250_tx_byte(TTYSx_BASE, 'B');
uart8250_tx_byte(TTYSx_BASE, ')');
uart8250_tx_byte(TTYSx_BASE, ' ');
Modified: coreboot-v3/mainboard/Kconfig
===================================================================
--- coreboot-v3/mainboard/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -40,8 +40,7 @@
config VENDOR_AMP
bool "AMP"
help
- Select this option for various systems from
- Advanced Micro Devices, Inc.
+ Select this option for various systems from AMP.
config VENDOR_ARTECGROUP
bool "Artec Group"
@@ -49,9 +48,9 @@
Select this option for various systems from the Artec Group.
config VENDOR_GIGABYTE
- bool "Gigabyte"
+ bool "GIGABYTE"
help
- Select this option for various systems from Gigabyte
+ Select this option for various systems from GIGABYTE.
config VENDOR_EMULATION
bool "Emulated systems"
Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/amd/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -56,7 +56,7 @@
select SUPERIO_WINBOND_W83627HF
select IOAPIC
help
- AMD Serengeti
+ AMD Serengeti development board.
endchoice
Modified: coreboot-v3/mainboard/amp/Kconfig
===================================================================
--- coreboot-v3/mainboard/amp/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/amp/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -33,7 +33,7 @@
select SUPERIO_ITE_IT8716F
select PIRQ_TABLE
help
- AMP TinyGX
+ AMP TinyGX board.
endchoice
Modified: coreboot-v3/mainboard/gigabyte/Kconfig
===================================================================
--- coreboot-v3/mainboard/gigabyte/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -24,7 +24,7 @@
depends on VENDOR_GIGABYTE
config BOARD_GIGABYTE_M57SLI
- bool "M57SLI"
+ bool "GA-M57SLI-S4"
select ARCH_X86
select OPTION_TABLE
select CPU_AMD_K8
@@ -33,7 +33,7 @@
select SUPERIO_ITE_IT8716F
select IOAPIC
help
- Gigabyte M57SLI
+ GIGABYTE GA-M57SLI-S4.
endchoice
Modified: coreboot-v3/mainboard/pcengines/Kconfig
===================================================================
--- coreboot-v3/mainboard/pcengines/Kconfig 2008-10-01 17:54:56 UTC (rev 878)
+++ coreboot-v3/mainboard/pcengines/Kconfig 2008-10-01 18:29:22 UTC (rev 879)
@@ -24,7 +24,7 @@
depends on VENDOR_PCENGINES
config BOARD_PCENGINES_ALIX1C
- bool "ALIX1.C"
+ bool "ALIX.1C"
select ARCH_X86
select CPU_AMD_GEODELX
select OPTION_TABLE
@@ -33,7 +33,7 @@
select SUPERIO_WINBOND_W83627HF
select PIRQ_TABLE
help
- PC Engines ALIX1.C.
+ PC Engines ALIX.1C.
config BOARD_PCENGINES_ALIX2C3
bool "ALIX.2C3"
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