[coreboot] [PATCH] flashrom: more accurate debug output and other trival changes
FENG Yu Ning
fengyuning1984 at gmail.com
Sat Nov 29 15:54:35 CET 2008
For more information, see ich7 spec(order no. 307013) section 21.1.1 .
Signed-off-by: FENG yu ning <fengyuning1984 at gmail.com>
Index: flashrom/ichspi.c
===================================================================
--- flashrom/ichspi.c (revision 3781)
+++ flashrom/ichspi.c (working copy)
@@ -77,7 +77,7 @@
#define ICH7_REG_SPIS 0x00 /* 16 Bits */
#define SPIS_SCIP 0x00000001
#define SPIS_CDS 0x00000004
-#define SPIS_FCERR 0x00000008
+#define SPIS_BAS 0x00000008
/* VIA SPI is compatible with ICH7, but maxdata
to transfer is 16 bytes.
@@ -268,8 +268,8 @@
/* Assemble SPIS */
temp16 = 0;
- /* clear error status registers */
- temp16 |= (SPIS_CDS + SPIS_FCERR);
+ /* clear bits indicating command completion status */
+ temp16 |= (SPIS_CDS + SPIS_BAS);
REGWRITE16(ICH7_REG_SPIS, temp16);
/* Assemble SPIC */
@@ -322,8 +322,8 @@
printf_debug("timeout\n");
}
- if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
- printf_debug("Transaction error!\n");
+ if ((REGREAD16(ICH7_REG_SPIS) & SPIS_BAS) != 0) {
+ printf_debug("Access blocked!\n");
return 1;
}
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