[coreboot] [PATCH] flashrom: Differentiate SPI errors

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Thu Nov 27 18:45:29 CET 2008


There are various reasons why a SPI command can fail. Amon others, I
have seen the following problems:
- The SPI opcode is not supported by the controller. ICH-style
controllers exhibit this if SPI config is locked down.
- The address in in a prohibited area. This can happen on ICH for any
access (BBAR) and for writes in chipset write protected areas.
- There is no SPI controller.

Introduce separate error codes for unsupported opcode and prohibited
address.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-ichspi_better_errorcodes/spi.h
===================================================================
--- flashrom-ichspi_better_errorcodes/spi.h	(revision 3773)
+++ flashrom-ichspi_better_errorcodes/spi.h	(working copy)
@@ -90,4 +90,8 @@
 #define JEDEC_BYTE_PROGRAM_OUTSIZE	0x05
 #define JEDEC_BYTE_PROGRAM_INSIZE	0x00
 
+/* Error codes */
+#define SPI_INVALID_OPCODE	2
+#define SPI_INVALID_ADDRESS	3
+
 #endif		/* !__SPI_H__ */
Index: flashrom-ichspi_better_errorcodes/ichspi.c
===================================================================
--- flashrom-ichspi_better_errorcodes/ichspi.c	(revision 3773)
+++ flashrom-ichspi_better_errorcodes/ichspi.c	(working copy)
@@ -632,7 +632,7 @@
 	/* unknown / not programmed command */
 	if (opcode_index == -1) {
 		printf_debug("Invalid OPCODE 0x%02x\n", cmd);
-		return 1;
+		return SPI_INVALID_OPCODE;
 	}
 
 	opcode = &(curopcodes->opcode[opcode_index]);


-- 
http://www.hailfinger.org/





More information about the coreboot mailing list