[coreboot] v3 CAR/ROM area collision on C7 and Core2Duo

Rudolf Marek r.marek at assembler.cz
Wed Nov 26 23:02:53 CET 2008

> 0xFEC00000 as well. That location is 20 MB below 4GB and the lowest

0xFEC0_0000 may be fixed location IO APIC. Other possible locations are 
0xFECX_YZ00 (not that 0xFEC cannot be changed)
0xFEEx_xxxx are internal APIC cycles for IRQ (MSI)

FEC0_0000 - FEC7_FFFF VIA APIC in SB (fixed)

FED4_4000 - FED4_FFFF trusted platform module MEM decode (fixed)


More information about the coreboot mailing list