[coreboot] r1055 - coreboot-v3/arch/x86/intel/core2

[svn at coreboot.org]

Author: stepan
Date: 2008-11-25 23:51:15 +0100 (Tue, 25 Nov 2008)
New Revision: 1055

Modified:
   coreboot-v3/arch/x86/intel/core2/stage0.S
Log:
get into ram init on kontron board.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: coreboot-v3/arch/x86/intel/core2/stage0.S
===================================================================
--- coreboot-v3/arch/x86/intel/core2/stage0.S	2008-11-25 22:39:00 UTC (rev 1054)
+++ coreboot-v3/arch/x86/intel/core2/stage0.S	2008-11-25 22:51:15 UTC (rev 1055)
@@ -161,7 +161,10 @@
 	movl	%esp, %ebp
 	pushl	%eax
 
+#if 0
+	/* this will be interpreted as failed bist */
 	port80_post(0x23)
+#endif
 
 	call	stage1_phase1