[coreboot] Fwd: HT chains fixup

Myles Watson mylesgw at gmail.com
Thu Nov 20 18:54:58 CET 2008

On 11/20/08, Myles Watson <mylesgw at gmail.com> wrote:
> On Thu, Nov 20, 2008 at 10:17 AM, Marc Jones <marcj303 at gmail.com> wrote:
>>  On Wed, Nov 19, 2008 at 9:16 PM, Myles Watson <mylesgw at gmail.com> wrote:
>> >> What is gained by knowing the ht path?
>> > When a HT chain is powered on, all the devices have the same UnitID (0)
>> > The subordinate busses get assigned bus numbers in the order that they
>> are
>> > found by PCI scan, but they are found in the order of the chain.  As you
>> > assign each a device number, another device is visible at device 0 until
>> the
>> > end of the chain is found.
>> >
>> Right, But I think that unitid setting happens before device scanning
>> and the dts is available. Once they are set there is no reason to
>> change them. The only thing is that the pci bridge code
> This is part of the confusing part.  UnitIDs get set early so that the
> serial port works.  I haven't gone through that code much yet, but it should
> only set up the southbridge link.  That gets reset later when the chains are
> being enumerated with the dts. This is the "collapsing" we talked about in
> an earlier thread.  In other words, when enumeration starts, all HT
> enumeration is blown away.

Of course I meant all non-coherent HT enumeration.  The coherent stuff isn't
being touched in this part.  That's also why the cpus aren't on ht links in
the dts.

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20081120/092ed099/attachment.html>

More information about the coreboot mailing list