[coreboot] [PATCH] Athlon64 K8 fixes

[Robert Millan]

On Wed, Nov 19, 2008 at 03:32:26PM -0800, ron minnich wrote:
> On Wed, Nov 19, 2008 at 3:01 PM, Robert Millan <rmh at aybabtu.com> wrote:
> >
> > Hi,
> >
> > My Athlon64 / K8 socket 939 setup needed the following adjustments to fix
> > memory read/write errors.  Thanks to Rudolf for hinting on which bits I
> > should check for.  Details:
> >
> >  - bit 9, mandated by spec to always be set on sodimm or socket 939 dual
> >   dimm.
> >
> >  - bit 28, enable 2T timing.  no idea why, but I get memory errors without
> >   it.
> >
> >  - bit 29, upper chip select.  mandated by spec on socket 939.
> >
> > My patch also adds missing descriptions, based on the ones from the spec
> > (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.pdf)
> >
> 
> Given that these settings are mainboard and socket dependent, we need
> a way to do these settings that takes those factors into account.
> 
> It seems to me that setting 2T on very athlon64 platform is not the
> way to do it.
> 
> Thanks for finding this and getting us this initial patch. Do you
> think you can extend it in some way so we don't slow down all k8
> platforms?

Okay.  Bit 29 is the easiest, as the spec reads "This bit should be set
if the 939 package is used."  This is enough for a single-DIMM setup to
work.

-- 
Robert Millan

  The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
  how) you may access your data; but nobody's threatening your freedom: we
  still allow you to remove your data and not access it at all."
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