[coreboot] r1046 - coreboot-v3/southbridge/amd/amd8132

[svn at coreboot.org]

Author: myles
Date: 2008-11-19 04:11:52 +0100 (Wed, 19 Nov 2008)
New Revision: 1046

Modified:
   coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
Log:
This patch fixes the 8132 so that it can use a 40-bit address space and so
that it uses the correct functions.  Using the device functions on the bridge
was not so good for it.

Signed-off-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c	2008-11-19 03:05:33 UTC (rev 1045)
+++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c	2008-11-19 03:11:52 UTC (rev 1046)
@@ -309,13 +309,11 @@
 	return;
 }
 
-#define BRIDGE_40_BIT_SUPPORT 0
-#if BRIDGE_40_BIT_SUPPORT
 static void bridge_read_resources(struct device *dev)
 {
 	struct resource *res;
 	pci_bus_read_resources(dev);
-	res = find_resource(dev, PCI_MEMORY_BASE);	
+	res = probe_resource(dev, PCI_MEMORY_BASE);	
 	if (res) {
 		res->limit = 0xffffffffffULL;
 	}
@@ -340,11 +338,10 @@
 		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
 		pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
 
-		report_resource_stored(dev, res, "");
+		report_resource_stored(dev, res, "including NPUML");
 	}
 	pci_dev_set_resources(dev);
 }
-#endif /* BRIDGE_40_BIT_SUPPORT */
 
 struct device_operations amd8132_pcix = {
 	.id = {.type = DEVICE_ID_PCI,
@@ -353,16 +350,11 @@
 	.constructor		 = default_device_constructor,
 	.reset_bus		 = pci_bus_reset,
 	.phase3_scan		 = amd8132_scan_bridge,
-#if BRIDGE_40_BIT_SUPPORT
 	.phase4_read_resources	 = bridge_read_resources,
 	.phase4_set_resources	 = bridge_set_resources,
-#else
-	.phase4_read_resources	 = pci_bus_read_resources,
-	.phase4_set_resources	 = pci_dev_set_resources,
-#endif
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = amd8132_pcix_init,
-	.ops_pci		 = &pci_dev_ops_pci,
+	.ops_pci		 = &pci_bus_ops_pci,
 };
 
 
@@ -429,6 +421,7 @@
 	.phase3_chip_setup_dev	 = ioapic_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
+	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = amd8132_ioapic_init,
 	.ops_pci		 = &pci_ops_pci_dev,
 };