[coreboot] r1019 - in coreboot-v3: arch/x86 arch/x86/intel/core2 arch/x86/via mainboard/jetway/j7f2 mainboard/kontron/986lcd-m southbridge/intel/i82801gx
svn at coreboot.org
svn at coreboot.org
Fri Nov 14 06:05:24 CET 2008
Author: rminnich
Date: 2008-11-14 06:05:24 +0100 (Fri, 14 Nov 2008)
New Revision: 1019
Added:
coreboot-v3/arch/x86/intel/core2/stage1.c
Modified:
coreboot-v3/arch/x86/Makefile
coreboot-v3/arch/x86/via/stage1.c
coreboot-v3/mainboard/jetway/j7f2/stage1.c
coreboot-v3/mainboard/kontron/986lcd-m/initram.c
coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c
coreboot-v3/southbridge/intel/i82801gx/libsmbus.c
Log:
Add core2 stage1.c dependency
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!
Index: arch/x86/via/stage1.c
Add empty stop_ap()
Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/arch/x86/Makefile 2008-11-14 05:05:24 UTC (rev 1019)
@@ -125,7 +125,7 @@
else
ifeq ($(CONFIG_CPU_INTEL_CORE2),y)
STAGE0_CAR_OBJ = intel/core2/stage0.o
- #STAGE0_ARCH_X86_SRC += intel/core2/stage1.c
+ STAGE0_ARCH_X86_SRC += intel/core2/stage1.c
else
ifeq ($(CONFIG_CPU_VIA_C7),y)
STAGE0_CAR_OBJ = via/stage0.o
Added: coreboot-v3/arch/x86/intel/core2/stage1.c
===================================================================
--- coreboot-v3/arch/x86/intel/core2/stage1.c (rev 0)
+++ coreboot-v3/arch/x86/intel/core2/stage1.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <msr.h>
+#include <macros.h>
+#include <cpu.h>
+#include <stage1.h>
+#include <globalvars.h>
+#include <string.h>
+#include <mtrr.h>
+
+/**
+ * Disable Cache As RAM (CAR) after memory is setup.
+ */
+void disable_car(void)
+{
+ printk(BIOS_DEBUG, "disable_car entry\n");
+ /* Determine new global variable location. Stack organization from top
+ * Top 4 bytes are reserved
+ * Pointer to global variables
+ * Global variables
+ *
+ * Align the result to 8 bytes
+ */
+ struct global_vars *const newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7);
+ /* Copy global variables to new location. */
+ memcpy(newlocation, global_vars(), sizeof(struct global_vars));
+ printk(BIOS_DEBUG, "disable_car global_vars copy done\n");
+ /* Set the new global variable pointer. */
+ *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation;
+
+ printk(BIOS_DEBUG, "disable_car global_vars pointer adjusted\n");
+ printk(BIOS_DEBUG, "entering asm code now\n");
+
+ __asm__ __volatile__(
+ " movl %[newesp], %%esp \n"
+
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ " movl %%cr0, %%eax \n"
+ " orl $(0x1<<30),%%eax \n"
+ " movl %%eax, %%cr0 \n"
+
+ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+ /* clear sth */
+ " xorl %%eax, %%eax \n"
+ " xorl %%edx, %%edx \n"
+ " movl $0x201, %%ecx \n"
+ " wrmsr \n"
+ " movl $0x200, %%ecx \n"
+ " wrmsr \n"
+
+ /* Set the default memory type and disable fixed and enable variable MTRRs */
+ " movl %[_MTRRdefType_MSR], %%ecx \n"
+ " xorl %%edx, %%edx \n"
+ /* Enable Variable and Disable Fixed MTRRs */
+ " movl $0x00000800, %%eax \n"
+ " wrmsr \n"
+
+ /* enable cache */
+ " movl %%cr0, %%eax \n"
+ " andl $0x9fffffff,%%eax \n"
+ " movl %%eax, %%cr0 \n"
+
+ " wbinvd \n"
+
+ " call stage1_phase3 \n"
+ :: [newesp] "i" (newlocation),
+ [_MTRRdefType_MSR] "i" (MTRRdefType_MSR)
+ : "memory");
+}
+
+void stop_ap(void)
+{
+}
+
Modified: coreboot-v3/arch/x86/via/stage1.c
===================================================================
--- coreboot-v3/arch/x86/via/stage1.c 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/arch/x86/via/stage1.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -90,3 +90,8 @@
[_MTRRdefType_MSR] "i" (MTRRdefType_MSR)
: "memory");
}
+
+void stop_ap(void)
+{
+}
+
Modified: coreboot-v3/mainboard/jetway/j7f2/stage1.c
===================================================================
--- coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -28,12 +28,6 @@
#include <superio/fintek/f71805f/f71805f.h>
#include <northbridge/via/cn700/cn700.h>
-/* Placeholders, build fails without them */
-void stop_ap(void)
-{
- //int noop;
-}
-
void hardware_stage1(void)
{
u32 dev;
Modified: coreboot-v3/mainboard/kontron/986lcd-m/initram.c
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -33,7 +33,6 @@
#include <string.h>
#include <msr.h>
#include <io.h>
-#include <amd/k8/k8.h>
#include <mc146818rtc.h>
#include <spd.h>
@@ -73,6 +72,92 @@
return do_smbus_read_byte(device, address);
}
+static void early_ich7_init(void)
+{
+ u8 reg8;
+ u32 reg32;
+
+ // program secondary mlt XXX byte?
+ pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ //RCBA32(0x0014) = 0x80000001;
+ //RCBA32(0x001c) = 0x03128010;
+
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042210;
+ /* Device 1d interrupt pin register */
+ RCBA32(0x310c) = 0x00214321;
+
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0132;
+ RCBA16(0x3142) = 0x3241;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3210;
+ RCBA16(0x3148) = 0x3210;
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
+ /* Disable unused devices */
+ RCBA32(0x3418) = 0x000e0063;
+
+ /* Enable PCIe Root Port Clock Gate */
+ // RCBA32(0x341c) = 0x00000001;
+}
+
+
+
/**
* main for initram for the AMD DBM690T
* @param init_detected Used to indicate that we have been started via init
@@ -89,6 +174,11 @@
*/
int main(void)
{
+ void i945_early_initialization(void);
+ void enable_smbus(void);
+ int fixup_i945_errata(void);
+ void i945_late_initialization(void);
+
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
@@ -102,7 +192,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/mainboard/kontron/986lcd-m/stage1_debug.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -25,7 +25,6 @@
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
-#include <statictree.h>
#include <config.h>
#define SMBUS_MEM_DEVICE_START 0x50
Modified: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-13 17:55:39 UTC (rev 1018)
+++ coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-14 05:05:24 UTC (rev 1019)
@@ -32,8 +32,8 @@
#include "i82801gx.h"
/* this is very chipset-specific. */
-#define SMBUS_TIMEOUT (100*1000*10)
/* These are common functions used in stage 1 and stage2 */
+#warning why do we have an smbus_delay here
void smbus_delay(void)
{
inb(0x80);
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