[coreboot] [PATCH 4/5] artecgroup/dbe61: Get DBE61A RAM setup and timing working.

[Mart Raudsepp]

Ühel kenal päeval, N, 2008-11-13 kell 18:27, kirjutas Carl-Daniel
Hailfinger:
> On 13.11.2008 01:19, Mart Raudsepp wrote:
> > artecgroup/dbe61: Get DBE61A RAM setup and timing working.
> >
> > * Uncomment the dbe61a SPD table
> > * Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc Jones
> > * In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that returns a greater than zero verify error count set up 128MB for DBE61A instead
> > * Tweak the dbe61a SPD table to result in LX MSR values as known to work in Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS halved, and some timings tweaked according to the v2 results.
> >
> > Now memtest86+ is quite happy on both DBE61C and DBE61A.
> >
> > Note that it should be better to ram_check in the high memory areas, but that doesn't seem to currently work.
> > Low memory check seems fine for the immediate time being, as the results appear shifted there as well with the wrong size/timing setup.
> >
> > Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
> >   
> 
> Good enough for now.
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Patches 1 to 4 are now in SVN then, thanks all.
r1014, r1015, r1016 and r1018.

DBE61 should now be bootable then :)

I will rework the fifth patch later on, and I believe Carl-Daniel is
investigating the ram_check on high memory issue - and I'll try to
compare with the v2 code of ours as well soon if there is no solution by
then.


Regards,
Mart Raudsepp
Artec Design LLC