[coreboot] Is this a correct way to read PCI control space register?

Peter Stuge peter at stuge.se
Wed Nov 12 17:26:03 CET 2008


FENG Yu Ning wrote:
> # lspci -xxxnns 0:0.0
> 00:00.0 Host bridge [0600]: Intel Corporation 945G/GZ/P/PL Express
> Memory Controller Hub [8086:2770]
> 00: 86 80 70 27 06 00 90 20 00 00 00 06 00 00 00 00
      00 01 02 03 04 05 06 07 08
..

> e0: 09 00 09 71 cb e1 9b 98 07 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
> 
> It is the byte at offset 8 makes me questioning. It is the revision
> identification register. This machine has a 945PL nb. According to
> Intel's doc(945x specification update 307503-010), the register
> should have a value of 82. Am I making mistake?

Nope, it seems the docs are wrong then.


> BTW, is the 0xe7 byte, with a value of '98', the same byte as the
> 'reg8' in the following excerpt of
> v3/northbridge/intel/i945/stage1.c?
> 
> static void i945_detect_chipset(void)
> {
> 	u8 reg8;
> 
> 	printk(BIOS_INFO, "\n");
> 	reg8 = (pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), 0xe7) & 0x70) >> 4;

Yes. reg8 would have 0x9 here.


//Peter




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