[coreboot] [PATCH] v3: Fix up PCI device code

Myles Watson mylesgw at gmail.com
Wed Nov 5 04:12:51 CET 2008



> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Carl-Daniel Hailfinger
> Sent: Tuesday, November 04, 2008 8:02 PM
> To: Coreboot
> Subject: [coreboot] [PATCH] v3: Fix up PCI device code
> 
> The current PCI device code calls pci_scan_bus with a PCI domain instead
> of a PCI bus as parameter. That causes all sorts of havoc, including
> double initialization of hardware and ignoring devices in the dts.
> 
> This patch attempts to fix these bugs, but it has other side effects.
> Somehow, resource allocation is now skipped.
> 
> I'd appreciate logs with and without this patch for every target,
> especially K8.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> 
> Index: corebootv3-pci_scan_bus_nexttry_minimal_fixup/device/pci_device.c
> ===================================================================
> --- corebootv3-pci_scan_bus_nexttry_minimal_fixup/device/pci_device.c
> 	(Revision 980)
> +++ corebootv3-pci_scan_bus_nexttry_minimal_fixup/device/pci_device.c
> 	(Arbeitskopie)
> @@ -1234,8 +1234,24 @@
>  unsigned int pci_domain_scan_bus(struct device *dev, unsigned int
> curr_bus)
>  {
>  	printk(BIOS_SPEW, "pci_domain_scan_bus: calling pci_scan_bus\n");
> -	/* There is only one link on this device, and it is always link 0.
> */
> -	return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, curr_bus);
> +	/* There is only one link on a bus, and it is always link 0.
> +	 * dev->link[0] for a PCI domain is the domain link.
> +	 * The child of the domain link is the PCI bus device.

This is where it gets a little strange.  The domain has lots of children,
but none of them are a "pci bus device."  If you look at Stefan's old pngs
from v2, there were a lot more devices and children than there are in v3 so
far.  I think looking at the output of show_all_devs makes this clear.  Any
log that's been posted to the link will have that.

I'm still trying to understand the pci enumeration, which is why I was
cleaning up the pci_device code.

Thanks,
Myles





More information about the coreboot mailing list