[coreboot] [PATCH] CN700/VT8237R stage2

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Nov 4 15:58:40 CET 2008

On 01.11.2008 22:28, Carl-Daniel Hailfinger wrote:
> On 01.11.2008 20:11, Carl-Daniel Hailfinger wrote:
>> On 01.11.2008 18:56, Corey Osgood wrote:
>>> System reset seems to occur between 2 and 3, both of those logs attached,
>>> along with arch/x86/via/stage1.o With HALT_AFTER=3, the post code keeps
>>> changing, as expected with the system rebooting, with HALT_AFTER=2 it was
>>> 0xc2.
>> Great results, thanks a lot!
>> One bug spotted and fixed. Can you retest with the same method and the
>> updated patch attached to this mail? I hope it will die much later,
>> perhaps at HALT_AFTER=13 or so.
> Thanks for the information that HALT_AFTER=5 is the last working setting.

OK, I reread every line of the code and reimplemented the problematic
stuff from scratch.

Can you try the new patch with HALT_AFTER=5 and 6? I'm pretty confident
that if 6 works, all later numbers should also not reboot.
By the way, the new code should be even better than the (working) v2 code.



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