[coreboot] [PATCH] CN700/VT8237R stage2

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sat Nov 1 20:11:45 CET 2008

On 01.11.2008 18:56, Corey Osgood wrote:
> System reset seems to occur between 2 and 3, both of those logs attached,
> along with arch/x86/via/stage1.o With HALT_AFTER=3, the post code keeps
> changing, as expected with the system rebooting, with HALT_AFTER=2 it was
> 0xc2.

Great results, thanks a lot!
One bug spotted and fixed. Can you retest with the same method and the
updated patch attached to this mail? I hope it will die much later,
perhaps at HALT_AFTER=13 or so.



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