[coreboot] ram init help on the i82830

Corey Osgood corey.osgood at gmail.com
Thu May 29 07:50:16 CEST 2008


Oh yeah, did you try leaving the dual sided stuff in there, and just
changing that one line (per my original fix)? Might be I was wrong (it
does happen, all too often).

-Corey

On Thu, May 29, 2008 at 1:46 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> I'm not sure about the problem, try a ram_check just to confirm it's
> bum ram, and see if you can pinpoint where it's bad.
>
>>        /* See if there are 2 sticks. */
>>        if((drb1 != 0) && (drb3 != 0)) {
>
> Should be:
>
> if((drb1 != 0) && (drb3 != drb1))
>
> -Corey
>
> On Thu, May 29, 2008 at 1:29 AM, Joseph Smith <joe at settoplinux.org> wrote:
>>
>> Well I changed it around a bit, here is what I came up with:
>>
>> static void do_ram_command(const struct mem_controller *ctrl, uint32_t
>> command,
>>                           uint32_t addr_offset)
>> {
>>        int i;
>>        uint8_t drb1, drb3;
>>        uint32_t reg32;
>>
>>        /* Configure the RAM command. */
>>        reg32 = pci_read_config32(ctrl->d0, DRC);
>>        /* Clear bits 29, 10-8, 6-4. */
>>        reg32 &= 0xdffff88f;
>>        reg32 |= command << 4;
>>
>>        drb1 = pci_read_config8(ctrl->d0, DRB + 1);
>>        drb3 = pci_read_config8(ctrl->d0, DRB + 3);
>>
>>        /* See if there are 2 sticks. */
>>        if((drb1 != 0) && (drb3 != 0)) {
>>                /* If RAM_COMMAND_NORMAL set the refresh mode. */
>>                if (command == RAM_COMMAND_NORMAL)
>>                        reg32 |= (RAM_COMMAND_REFRESH << 8);
>>                pci_write_config32(ctrl->d0, DRC, reg32);
>>
>>                /* Send ram commands to DIMM0. */
>>                read32(0 + addr_offset);
>>                PRINT_DEBUG("    Sending RAM command DIMM0 0x");
>>                PRINT_DEBUG_HEX32(reg32);
>>                PRINT_DEBUG(" to 0x");
>>                PRINT_DEBUG_HEX32(0 + addr_offset);
>>                PRINT_DEBUG("\r\n");
>>
>>                /* If RAM_COMMAND_NORMAL set the IC bit. */
>>                if (command == RAM_COMMAND_NORMAL)
>>                        reg32 |= (RAM_COMMAND_IC << 29);
>>                pci_write_config32(ctrl->d0, DRC, reg32);
>>                /* Send ram commands to DIMM1. */
>>                read32((drb1 * 32 * 1024 * 1024) + addr_offset);
>>                PRINT_DEBUG("    Sending RAM command DIMM1 0x");
>>                PRINT_DEBUG_HEX32(reg32);
>>                PRINT_DEBUG(" to 0x");
>>                PRINT_DEBUG_HEX32((drb1 * 32 * 1024 * 1024) + addr_offset);
>>                PRINT_DEBUG("\r\n");
>>        } else {
>>                /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
>>                if (command == RAM_COMMAND_NORMAL)
>>                        reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
>>                pci_write_config32(ctrl->d0, DRC, reg32);
>>
>>                read32(0 + addr_offset);
>>                PRINT_DEBUG("    Sending RAM command to DIMM at 0x");
>>                PRINT_DEBUG_HEX32(reg32);
>>                PRINT_DEBUG(" to 0x");
>>                PRINT_DEBUG_HEX32(0 + addr_offset);
>>                PRINT_DEBUG("\r\n");
>>       }
>>
>> }
>>
>> The process seems to do what it is supposed to but it is still craping out.
>> HELP??
>> Here is the bootlog:
>>
>> coreboot-2.0.0_IP1000 Thu May 29 00:58:25 EDT 2008 starting...
>> Setting initial registers....
>> Initial registers have been set.
>> Found DIMM in slot 00
>> DIMM is 0x0100 on side 1
>> DIMM is 0x0100 on side 2
>> DRB 0x60 has been set to 0x08
>> DRB1 0x61 has been set to 0x10
>> Found DIMM in slot 01
>> DIMM is 0x0040 on side 1
>> DIMM is 0x0000 on side 2
>> DRB2 0x62 has been set to 0x12
>> DRB3 0x63 has been set to 0x12
>> Found DIMM in slot 00, setting DRA...
>> DRA 0x70 has been set to 0x08
>> Found DIMM in slot 01, setting DRA...
>> DRA 0x71 has been set to 0xf1
>> RAM Enable 1: Apply NOP
>>    Sending RAM command DIMM0 0x00000010 to 0x00000000
>>    Sending RAM command DIMM1 0x00000010 to 0x20000000
>> RAM Enable 2: Precharge all
>>    Sending RAM command DIMM0 0x00000020 to 0x00000000
>>    Sending RAM command DIMM1 0x00000020 to 0x20000000
>> RAM Enable 3: CBR
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>>    Sending RAM command DIMM0 0x00000060 to 0x00000000
>>    Sending RAM command DIMM1 0x00000060 to 0x20000000
>> RAM Enable 4: Mode register set
>>    Sending RAM command DIMM0 0x00000030 to 0x000001d0
>>    Sending RAM command DIMM1 0x00000030 to 0x200001d0
>> RAM Enable 5: Normal operation
>>    Sending RAM command DIMM0 0x00000270 to 0x00000000
>>    Sending RAM command DIMM1 0x20000270 to 0x20000000
>> Northbridge following SDRAM init:
>> PCI: 00:00.00
>> 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00
>> 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
>> 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
>> 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33
>> 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
>> 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20
>> 80: 00 00 00 00 00 00 00 00 80 60 33 0b 00 00 00 00
>> 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
>> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
>> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>> e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
>> f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc
>> Copying coreboot to RAM.
>> Jumping to coreboot.
>>
>> ####LOCKS UP HERE####
>>
>> What am I doing wrong?
>> --
>> Thanks,
>> Joseph Smith
>> Set-Top-Linux
>> www.settoplinux.org
>>
>>
>




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