[coreboot] Geode LX: PLL initialization in coreboot-v2

Marc Jones marc.jones at amd.com
Wed May 28 17:50:48 CEST 2008

llandre wrote:
>>> I can't understand how the GLCP_SYS_RSTPLL register is set on DB800. 
>>> The strapping pins of the DB800 IRQ13,PW0,SUSPA#,GNT#[2:0] are all 
>>> '0' and PW1 is '1'. Before the PLLs are configured, I can see on the 
>>> console: "GLCP_SYS_RSTPLL (4c000014) value is: 000003d7:00001880". 
>>> The last byte 0x80 confirms the strapping pins settings, but the PLL 
>>> multipliers are already set (COREMULT = 11, GLIUMULT = 7, COREDIV and 
>>> GLIUDIV set, so CPU freq = 400MHz and memory DDR266). Where are these 
>>> values set ?
>> The CPU comes up in bypass mode but the multipliers are set to a 
>> default value. On the pll reset the default settings takes effect. In 
>> the databook, look at Table 6-87. The first line shows the bypass 
>> setting without PW1 set.
> Ok, so COREMULT = 11, GLIUMULT = 7 are the default settings (row #1 of 
> table 6-87) since PW0,SUSPA#,GNT#[2:0] are all '0'. From table 6-88, the 
> status of IRQ13 doesn't care for COREMULT and GLIUMULT. The same happens 
> for PW1, since it is read during reset and it is wired to COREDIV and 
> GLDIV. Is it correct ?


> The conclusion is that, with the default configuration (strapping pins 
> PW0,SUSPA#,GNT#[2:0] = '0' and with ManualConf = 0), the DB800 is 
> underclocked for both CPU and RAM freq. Is it right ?

Yes (if you have faster cpu and memory)

> So if I want to use the board the board at its maximum frequency there 
> are two possibilities:
> 1) the hardware way: set the strapping pins to the correct values (for 
> example 500MHz for a LX800 and DDR400); inside pll_reset() I calculate 
> the value of COREMULT, GLIUMULT, COREDIV and GLIUDIV (just like table 
> 6-87) from BOOTSTRAPS (GLCP_SYS_RSTPLL[7:1]) and then I write them to 
> GLCP_SYS_RSTPLL before the reset.
> 2) the software way: I calculate the values of COREMULT, GLIUMULT, 
> COREDIV and GLIUDIV from CPU ID and RAM SPD and then I write them to 
> GLCP_SYS_RSTPLL before the reset.
> Do you agree ?


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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