[coreboot] Geode LX: PLL initialization in coreboot-v2

Marc Jones Marc.Jones at amd.com
Wed May 28 00:22:28 CEST 2008

llandre wrote:
> I can't understand how the GLCP_SYS_RSTPLL register is set on DB800. The 
> strapping pins of the DB800 IRQ13,PW0,SUSPA#,GNT#[2:0] are all '0' and 
> PW1 is '1'. Before the PLLs are configured, I can see on the console: 
> "GLCP_SYS_RSTPLL (4c000014) value is: 000003d7:00001880". The last byte 
> 0x80 confirms the strapping pins settings, but the PLL multipliers are 
> already set (COREMULT = 11, GLIUMULT = 7, COREDIV and GLIUDIV set, so 
> CPU freq = 400MHz and memory DDR266). Where are these values set ?

The CPU comes up in bypass mode but the multipliers are set to a default 
value. On the pll reset the default settings takes effect. In the 
databook, look at Table 6-87. The first line shows the bypass setting 
without PW1 set.

> On my hardware, when pll_reset is called, the automatic configuration is 
> used. If I try to use the manual configuration (#define ManualConf 1), 
> the board hangs after the CPU is reset from pll_reset.

What did you set PLLMSRhi and PLLMSRlo to? If you have PW1 set on your 
platform you need to have the MBDIV and COREDIV bits set.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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