[coreboot] legacybios update

Kevin O'Connor kevin at koconnor.net
Sun May 18 09:14:22 CEST 2008


I've just pushed a new elf payload to:


This version should be free of qemu dependencies.  In particular, it
no longer relies on parameters passed in nvram.  The code will still
access CMOS_RESET_CODE (0x0f), CMOS_FLOPPY_DRIVE_TYPE (0x10), and
CMOS_CENTURY (0x32).  However, I think these nvram locations are
pretty standard and basically harmless.

The above payload will not populate PIR, MPTABLE, SMBIOS, or ACPI
tables.  Also, just to facilitate testing, I've hardcoded the memory
to 128Megs, and I've hardcoded a standard boot order (floppy, cdrom,
then hard drive).

I've tested the payload with coreboot-v3 and qemu.  The above payload
plugs into the standard coreboot-v3 elf payload config.  I did not
customize the coreboot code at all - however, I did disable "Execute
PCI Option ROMs" in the coreboot config.  It looks like I'll need to
acquire some real hardware to test on.  Any suggestions?

Anyone willing to try the above on real hardware?  :-)


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