[coreboot] [PATCH] flashrom: restructure SPI support, part 2
Peter Stuge
peter at stuge.se
Tue May 13 16:46:38 CEST 2008
On Tue, May 13, 2008 at 04:17:57PM +0200, Carl-Daniel Hailfinger wrote:
> flashrom: Move the SPI #defines from spi.c to spi.h
> This patch has no code changes.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>
Simple patches are easy to ack. :)
> Index: flashrom-spirestructure/spi.c
> ===================================================================
> --- flashrom-spirestructure/spi.c (Revision 3301)
> +++ flashrom-spirestructure/spi.c (Arbeitskopie)
> @@ -27,71 +27,12 @@
> #include <stdint.h>
> #include <string.h>
> #include "flash.h"
> +#include "spi.h"
>
> #define ITE_SUPERIO_PORT1 0x2e
> #define ITE_SUPERIO_PORT2 0x4e
>
> -/* Read Electronic ID */
> -#define JEDEC_RDID 0x9f
> -#define JEDEC_RDID_OUTSIZE 0x01
> -#define JEDEC_RDID_INSIZE 0x03
>
> -/* Write Enable */
> -#define JEDEC_WREN 0x06
> -#define JEDEC_WREN_OUTSIZE 0x01
> -#define JEDEC_WREN_INSIZE 0x00
> -
> -/* Write Disable */
> -#define JEDEC_WRDI 0x04
> -#define JEDEC_WRDI_OUTSIZE 0x01
> -#define JEDEC_WRDI_INSIZE 0x00
> -
> -/* Chip Erase 0x60 is supported by Macronix/SST chips. */
> -#define JEDEC_CE_60 0x60
> -#define JEDEC_CE_60_OUTSIZE 0x01
> -#define JEDEC_CE_60_INSIZE 0x00
> -
> -/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
> -#define JEDEC_CE_C7 0xc7
> -#define JEDEC_CE_C7_OUTSIZE 0x01
> -#define JEDEC_CE_C7_INSIZE 0x00
> -
> -/* Block Erase 0x52 is supported by SST chips. */
> -#define JEDEC_BE_52 0x52
> -#define JEDEC_BE_52_OUTSIZE 0x04
> -#define JEDEC_BE_52_INSIZE 0x00
> -
> -/* Block Erase 0xd8 is supported by EON/Macronix chips. */
> -#define JEDEC_BE_D8 0xd8
> -#define JEDEC_BE_D8_OUTSIZE 0x04
> -#define JEDEC_BE_D8_INSIZE 0x00
> -
> -/* Sector Erase 0x20 is supported by Macronix/SST chips. */
> -#define JEDEC_SE 0x20
> -#define JEDEC_SE_OUTSIZE 0x04
> -#define JEDEC_SE_INSIZE 0x00
> -
> -/* Read Status Register */
> -#define JEDEC_RDSR 0x05
> -#define JEDEC_RDSR_OUTSIZE 0x01
> -#define JEDEC_RDSR_INSIZE 0x01
> -#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
> -
> -/* Write Status Register */
> -#define JEDEC_WRSR 0x01
> -#define JEDEC_WRSR_OUTSIZE 0x02
> -#define JEDEC_WRSR_INSIZE 0x00
> -
> -/* Read the memory */
> -#define JEDEC_READ 0x03
> -#define JEDEC_READ_OUTSIZE 0x04
> -/* JEDEC_READ_INSIZE : any length */
> -
> -/* Write memory byte */
> -#define JEDEC_BYTE_PROGRAM 0x02
> -#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
> -#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
> -
> uint16_t it8716f_flashport = 0;
> /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
> int fast_spi = 1;
> Index: flashrom-spirestructure/spi.h
> ===================================================================
> --- flashrom-spirestructure/spi.h (Revision 0)
> +++ flashrom-spirestructure/spi.h (Revision 0)
> @@ -0,0 +1,88 @@
> +/*
> + * This file is part of the flashrom project.
> + *
> + * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#ifndef __SPI_H__
> +#define __SPI_H__ 1
> +
> +/*
> + * Contains the generic SPI headers
> + */
> +
> +/* Read Electronic ID */
> +#define JEDEC_RDID 0x9f
> +#define JEDEC_RDID_OUTSIZE 0x01
> +#define JEDEC_RDID_INSIZE 0x03
> +
> +/* Write Enable */
> +#define JEDEC_WREN 0x06
> +#define JEDEC_WREN_OUTSIZE 0x01
> +#define JEDEC_WREN_INSIZE 0x00
> +
> +/* Write Disable */
> +#define JEDEC_WRDI 0x04
> +#define JEDEC_WRDI_OUTSIZE 0x01
> +#define JEDEC_WRDI_INSIZE 0x00
> +
> +/* Chip Erase 0x60 is supported by Macronix/SST chips. */
> +#define JEDEC_CE_60 0x60
> +#define JEDEC_CE_60_OUTSIZE 0x01
> +#define JEDEC_CE_60_INSIZE 0x00
> +
> +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
> +#define JEDEC_CE_C7 0xc7
> +#define JEDEC_CE_C7_OUTSIZE 0x01
> +#define JEDEC_CE_C7_INSIZE 0x00
> +
> +/* Block Erase 0x52 is supported by SST chips. */
> +#define JEDEC_BE_52 0x52
> +#define JEDEC_BE_52_OUTSIZE 0x04
> +#define JEDEC_BE_52_INSIZE 0x00
> +
> +/* Block Erase 0xd8 is supported by EON/Macronix chips. */
> +#define JEDEC_BE_D8 0xd8
> +#define JEDEC_BE_D8_OUTSIZE 0x04
> +#define JEDEC_BE_D8_INSIZE 0x00
> +
> +/* Sector Erase 0x20 is supported by Macronix/SST chips. */
> +#define JEDEC_SE 0x20
> +#define JEDEC_SE_OUTSIZE 0x04
> +#define JEDEC_SE_INSIZE 0x00
> +
> +/* Read Status Register */
> +#define JEDEC_RDSR 0x05
> +#define JEDEC_RDSR_OUTSIZE 0x01
> +#define JEDEC_RDSR_INSIZE 0x01
> +#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
> +
> +/* Write Status Register */
> +#define JEDEC_WRSR 0x01
> +#define JEDEC_WRSR_OUTSIZE 0x02
> +#define JEDEC_WRSR_INSIZE 0x00
> +
> +/* Read the memory */
> +#define JEDEC_READ 0x03
> +#define JEDEC_READ_OUTSIZE 0x04
> +/* JEDEC_READ_INSIZE : any length */
> +
> +/* Write memory byte */
> +#define JEDEC_BYTE_PROGRAM 0x02
> +#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
> +#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
> +
> +#endif /* !__SPI_H__ */
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