[coreboot] proposed patch, notsigned off, comments welcome.

ron minnich rminnich at gmail.com
Mon May 12 06:51:10 CEST 2008

The motivation for this tool is simple. Given a working system, tell
me what is hooked to what, IRQ- and PCI INT-wise. Or, given a
non-working system, go into the system and try to find things that
look wrong. At the very least, explain how the confusing thicket of LX
interrupts is wired up, because I sure as hell can't figure it out
most of the time. And, judging by our most recent fix, it even can
confound the experts :-)

In the limit, we ought to be able to run this tool on a working
system, compare it to a non-working system, and see what's different.

I don't actually see a difference from my end between an IRQ
(Interrupt request in old-speak) and a PCI INT (interrupt request in
old speak) but if you want to rename things, have at it. Code
attached, do your worst!

I will rename them too but at present I'm a lot more concerned with
tracking down whatever is set up wrong on the alix1c. Something is
just flat out wrong! We need to find it and I'm running out of time
with the Berlin show looming.

You have to talk to VRs because VSA talks VRs, and when you Do Certain
Things, VSA gets involved. So I am not inclined to ignore the VRs.

Here's the latest version of the program together with alix1c output.

input enable 0f7af085 invert 0xcf7e3081
irqmap from vr is 0xd0c0700
4d1:4d0 0e00
Filter events: 0/00 1/00 2/00 3/00 4/00 5/00 6/00 7/00
IRQ A, GPIO pin 0
Input Enabled and Inverted
IRQ B, GPIO pin 7
Input Enabled and Inverted
IRQ C, GPIO pin 12
Input Enabled and Inverted
IRQ D, GPIO pin 13
Input Enabled and Inverted

So notice that it appears when coreboot sets the VRs for INTAB and
INTCD, VSA is setting up the GPIOs as enabled and inverted. Useful to
know. Next steps are to see how the 22/23 registers are set up, and,
with luck, trace it all the way through and maybe even find the
problem. For now, however, the 3v PCI slot INTs are not working at
all, as far as I can tell. They're almost acting edge-triggered. I
think it's an artifact of sharing PCI INTs with the USB -- the
ethernet, which is attached in the same way (with the same wire!) as
the PCI slot, works just fine. It's very odd.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: lxirq.c
Type: text/x-csrc
Size: 4645 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20080511/8a84db54/attachment.c>

More information about the coreboot mailing list