[coreboot] r682 - in coreboot-v3/mainboard/pcengines: alix1c alix2c3

svn at coreboot.org svn at coreboot.org
Fri May 9 23:48:28 CEST 2008


Author: rminnich
Date: 2008-05-09 23:48:28 +0200 (Fri, 09 May 2008)
New Revision: 682

Modified:
   coreboot-v3/mainboard/pcengines/alix1c/dts
   coreboot-v3/mainboard/pcengines/alix2c3/dts
Log:
This is the fix for MFGPT on those boards which have a cs5536 and ALSO
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.

Thanks to Marc and Jordan for this one.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>



Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts	2008-05-09 16:12:41 UTC (rev 681)
+++ coreboot-v3/mainboard/pcengines/alix1c/dts	2008-05-09 21:48:28 UTC (rev 682)
@@ -36,9 +36,9 @@
 			/config/("southbridge/amd/cs5536/dts");
 			/* Interrupt enables for LPC bus.
 			 *  Each bit is an IRQ 0-15. */
-			lpc_serirq_enable = "0x000010da";
+			lpc_serirq_enable = "0x0000105A";
 			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
-			lpc_serirq_polarity = "0x0000EF25";
+			lpc_serirq_polarity = "0x0000EFA5";
 			/* 0:continuous 1:quiet */
 			lpc_serirq_mode = "1";
 			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 

Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/dts	2008-05-09 16:12:41 UTC (rev 681)
+++ coreboot-v3/mainboard/pcengines/alix2c3/dts	2008-05-09 21:48:28 UTC (rev 682)
@@ -34,9 +34,9 @@
 			/config/("southbridge/amd/cs5536/dts");
 			/* Interrupt enables for LPC bus.
 			 *  Each bit is an IRQ 0-15. */
-			lpc_serirq_enable = "0x000010da";
+			lpc_serirq_enable = "0x0000105A";
 			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
-			lpc_serirq_polarity = "0x0000EF25";
+			lpc_serirq_polarity = "0x0000EFA5";
 			/* 0:continuous 1:quiet */
 			lpc_serirq_mode = "1";
 			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 





More information about the coreboot mailing list