[coreboot] v3 IRQ table strangeness
c-d.hailfinger.devel.2006 at gmx.net
Fri May 9 00:30:31 CEST 2008
On 08.05.2008 05:50, ron minnich wrote:
> On Wed, May 7, 2008 at 7:09 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> is it intentional that irq_tables.h in all v3 AMD GeodeLX/CS5536 targets
>> lists the "NatSemi CS5535 ISA Bridge" at 00:0f.0 as interrupt router?
>> By the way, the dbe61 patch Mart sent tonight changes that for dbe61 to
>> the "CS5536 GeodeLink PCI South Bridge" at 00:12.0 as interrupt router.
> we can change it, the old name is historical
So PCI IDs and bus location of the interrupt router in the PIRQ table
have no meaning at all for Geode?
More information about the coreboot