[coreboot] r3282 - trunk/coreboot-v2/src/southbridge/amd/cs5536

[svn at coreboot.org]

Author: mjones
Date: 2008-05-06 18:56:47 +0200 (Tue, 06 May 2008)
New Revision: 3282

Modified:
   trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c
Log:
cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.

Signed-off-by: Marc Jones <marc.jones at amd.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>




Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c	2008-05-06 15:17:43 UTC (rev 3281)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c	2008-05-06 16:56:47 UTC (rev 3282)
@@ -43,7 +43,7 @@
 	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
 	ide_cfg = pci_read_config32(dev, IDE_CFG);
 	ide_cfg |= CHANEN | PWB;
-	pci_write_config8(dev, IDE_CFG, ide_cfg);
+	pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
 static void ide_enable(struct device *dev)