[coreboot] DBE62 status

[Mart Raudsepp]

Hello,

Now that ethernet works for me and I can ssh in (having no VGA BIOS and
no visible access otherwise other than serial console which I didn't
bother to get to work on my full USB HDD system for logins), here are
some of the remaining issues with DBE62 that I have noticed:


* lxfb and Xorg does not work, probably no video memory setup:
lxfb 0000:00:01.1: failed to map frame buffer or controller registers
lxfb: probe of 0000:00:01.1 failed with error -12

* The two USB ports on the right side don't power up

* NAND is set up on the wrong chip select (should be CS1, currently
hardcoded to CS0 in southbridge/cs5536/cs5536.c)

* PLL initialization should trust bootstraps


For the PLL initialization I intend to send a patch soon after some
testing and registry comparisons that sets MANUALCONF in raminit.c back
to 0

NAND setup needs some refactoring and allowing selection of the chip
select(s) in dts. There I am not sure if we should bother supporting
multiple NAND flashes or not. Theoretically I believe it to be possible,
but I don't know of any such boards and just know that linux 553x_nand
mtd driver seems to be capable of handling that scenario.
In the case of supporting only one, there could just be an additional
variable in dts that tells which chip select is used for NAND (how it is
wired up on the board). Otherwise I guess the new dts array support
would come into play?

I have no ideas about the USB ports at the moment. Will try to find time
to compare dmesg logs, registers and such things, maybe also some setup
problems.

Same about video memory, but that seems easy enough that I might
actually succeed.


There were some discussions about merging the DBE61 and DBE62 code, and
that might be a good course of action going forward. The differences
between these boards as I remember are

a) different ethernet adapter - not much concerning firmware, might have
a slightly different IRQ routing, but perhaps not, no working raminit
for DBE61 doesn't allow to easily find out.
b) different GeodeLink speed (PCI clock) - DBE61 has 33MHz, DBE62 66MHz
c) different memory chips - need different fake SPDs
d) LPC vs FWH boot ROM interface
e) dedicated serial port pins brought out (at least CTS, RTS, RX, TX) -
another UART, allowing always enabled serial console output without
sacrificing DDC


Given that, does it seem like a good or bad idea to merge them? There
isn't all that much code in mainboard folders, but DBE61 code at the
moment could probably use a mostly full code pull from DBE62 code, so a
good time to decide on that, it seems.



Regards,
Mart Raudsepp
Artec Design LLC