[coreboot] r3196 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/include/arch config mainboard/advantech/pcm-5820 mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/asi/mb_5blmp mainboard/axus/tc320 mainboard/bcom/winnet100 mainboard/digitallogic/msm800sev mainboard/eaglelion/5bcm mainboard/iei/juki-511p mainboard/iei/nova4899r mainboard/pcengines/alix1c southbridge/amd/cs5530 southbridge/amd/cs5536
svn at coreboot.org
svn at coreboot.org
Sat Mar 29 17:59:28 CET 2008
Author: uwe
Date: 2008-03-29 17:59:27 +0100 (Sat, 29 Mar 2008)
New Revision: 3196
Added:
trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_pirq.c
trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_pirq.c
Modified:
trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h
trunk/coreboot-v2/src/config/Options.lb
trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c
trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c
trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c
trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/irq_tables.c
trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
trunk/coreboot-v2/src/mainboard/pcengines/alix1c/irq_tables.c
trunk/coreboot-v2/src/southbridge/amd/cs5530/Config.lb
trunk/coreboot-v2/src/southbridge/amd/cs5536/Config.lb
Log:
Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov at gmail.com>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -1,6 +1,7 @@
#include <console/console.h>
#include <arch/pirq_routing.h>
#include <string.h>
+#include <device/pci.h>
#if (DEBUG==1 && HAVE_PIRQ_TABLE==1)
static void check_pirq_routing_table(struct irq_routing_table *rt)
@@ -94,6 +95,80 @@
memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
printk_info("done.\n");
verify_copy_pirq_routing_table(addr);
+ pirq_routing_irqs(addr);
return addr + intel_irq_routing_table.size;
}
#endif
+
+#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+void pirq_routing_irqs(unsigned long addr)
+{
+ int i, j, k, num_entries;
+ unsigned char irq_slot[4];
+ unsigned char pirq[4] = {0, 0, 0, 0};
+ struct irq_routing_table *pirq_tbl;
+ device_t pdev;
+
+ pirq_tbl = (struct irq_routing_table *)(addr);
+ num_entries = (pirq_tbl->size - 32) / 16;
+
+ /* Set PCI IRQs. */
+ for (i = 0; i < num_entries; i++) {
+
+ printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
+ pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot);
+
+ for (j = 0; j < 4; j++) {
+
+ int link = pirq_tbl->slots[i].irq[j].link;
+ int bitmap = pirq_tbl->slots[i].irq[j].bitmap & pirq_tbl->exclusive_irqs;
+ int irq = 0;
+
+ printk_debug("INT: %c link: %x bitmap: %x ",
+ 'A' + j, link, bitmap);
+
+ if (!bitmap|| !link || link > 4) {
+
+ printk_debug("not routed\n");
+ irq_slot[j] = irq;
+ continue;
+ }
+
+ /* yet not routed */
+ if (!pirq[link - 1]) {
+
+ for (k = 2; k < 15; k++) {
+
+ if (!((bitmap >> k) & 1))
+ continue;
+
+ irq = k;
+
+ /* yet not routed */
+ if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq)
+ break;
+ }
+
+ if (irq)
+ pirq[link - 1] = irq;
+ }
+ else
+ irq = pirq[link - 1];
+
+ printk_debug("IRQ: %d\n", irq);
+ irq_slot[j] = irq;
+ }
+
+ /* Bus, device, slots IRQs for {A,B,C,D}. */
+ pci_assign_irqs(pirq_tbl->slots[i].bus,
+ pirq_tbl->slots[i].devfn >> 3, irq_slot);
+ }
+
+ printk_debug("PIRQ1: %d\n", pirq[0]);
+ printk_debug("PIRQ2: %d\n", pirq[1]);
+ printk_debug("PIRQ3: %d\n", pirq[2]);
+ printk_debug("PIRQ4: %d\n", pirq[3]);
+
+ pirq_assign_irqs(pirq);
+}
+#endif
Modified: trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/pirq_routing.h 2008-03-29 16:59:27 UTC (rev 3196)
@@ -42,7 +42,13 @@
#if HAVE_PIRQ_TABLE==1
unsigned long copy_pirq_routing_table(unsigned long start);
unsigned long write_pirq_routing_table(unsigned long start);
+#if PIRQ_ROUTE==1
+void pirq_routing_irqs(unsigned long start);
+void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
#else
+#define pirq_routing_irqs(start) {}
+#endif
+#else
#define copy_pirq_routing_table(start) (start)
#define write_pirq_routing_table(start) (start)
#endif
Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/config/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -716,6 +716,11 @@
export used
comment "Define if we have a PIRQ table"
end
+define PIRQ_ROUTE
+ default 0
+ export used
+ comment "Define if we have a PIRQ table and want routing IRQs"
+end
define IRQ_SLOT_COUNT
default none
export used
Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -63,6 +63,7 @@
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -75,6 +76,7 @@
default ROM_SIZE = 256 * 1024
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
+default PIRQ_ROUTE = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -48,6 +48,7 @@
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=4
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/irq_tables.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -65,42 +65,5 @@
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -48,6 +48,7 @@
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/irq_tables.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -67,42 +67,5 @@
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -48,6 +48,7 @@
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,7 +85,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=3
-
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/irq_tables.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -64,42 +64,5 @@
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
-}
\ No newline at end of file
+ return copy_pirq_routing_table(addr);
+}
Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -42,8 +42,8 @@
# uses CONFIG_CONSOLE_VGA
# uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
-
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256 * 1024
@@ -71,6 +71,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5 # TODO?
+default PIRQ_ROUTE=1
##
## Build code to export a CMOS option table
Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -63,6 +63,7 @@
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
default HAVE_OPTION_TABLE = 0
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -63,6 +63,7 @@
uses CONFIG_SPLASH_GRAPHIC
uses CONFIG_GX1_VIDEO
uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
## We want to support up to 1024x768 at 16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
default HAVE_OPTION_TABLE = 0
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -48,6 +48,7 @@
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -84,6 +85,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/irq_tables.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/irq_tables.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -69,39 +69,7 @@
}
};
-
-unsigned long write_pirq_routing_table(unsigned long addr){
- int i, j, k, num_entries;
- unsigned int pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *)(addr);
- num_entries = (pirq_tbl->size - 32)/16;
-
- /* Set PCI IRQs */
- for (i=0; i < num_entries; i++){
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++){
- printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
- for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
- pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
- }
-
- /* put the PIR table in memory and checksum */
- return pirtable_end;
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
}
-
Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -42,6 +42,7 @@
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -75,6 +76,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -43,6 +43,7 @@
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -72,6 +73,7 @@
##
default HAVE_PIRQ_TABLE=0
default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -45,6 +45,7 @@
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -82,6 +83,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=7
+default PIRQ_ROUTE=1
#object irq_tables.o
##
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -68,6 +68,7 @@
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 512*1024
@@ -104,7 +105,7 @@
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
-
+default PIRQ_ROUTE=1
##
## Build code to export a CMOS option table
##
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/irq_tables.c 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/irq_tables.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -106,46 +106,5 @@
unsigned long write_pirq_routing_table(unsigned long addr)
{
- int i, j, k, num_entries;
- unsigned char pirq[4];
- uint16_t chipset_irq_map;
- uint32_t pciAddr, pirtable_end;
- struct irq_routing_table *pirq_tbl;
-
- pirtable_end = copy_pirq_routing_table(addr);
-
- /* Set up chipset IRQ steering. */
- pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
- printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
- chipset_irq_map);
- outl(pciAddr & ~3, 0xCF8);
- outl(chipset_irq_map, 0xCFC);
-
- pirq_tbl = (struct irq_routing_table *) (addr);
- num_entries = (pirq_tbl->size - 32) / 16;
-
- /* Set PCI IRQs. */
- for (i = 0; i < num_entries; i++) {
- printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
- for (j = 0; j < 4; j++) {
- printk_debug("INT: %c bitmap: %x ", 'A' + j,
- pirq_tbl->slots[i].irq[j].bitmap);
- /* Finds lsb in bitmap to IRQ#. */
- for (k = 0;
- (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
- && (pirq_tbl->slots[i].irq[j].bitmap != 0);
- k++);
- pirq[j] = k;
- printk_debug("PIRQ: %d\n", k);
- }
-
- /* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, pirq);
- }
-
- /* Put the PIR table in memory and checksum. */
- return pirtable_end;
+ return copy_pirq_routing_table(addr);
}
Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5530/Config.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Config.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -23,3 +23,4 @@
driver cs5530_isa.o
driver cs5530_ide.o
driver cs5530_vga.o
+driver cs5530_pirq.o
Added: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_pirq.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_pirq.c (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_pirq.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+ device_t pdev;
+
+ pdev = dev_find_device(PCI_VENDOR_ID_CYRIX,
+ PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0);
+
+ if (pdev) {
+ pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0]));
+ pci_write_config8(pdev, 0x5d, (pIntAtoD[3] << 4 | pIntAtoD[2]));
+ }
+}
+#endif
Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/Config.lb 2008-03-29 16:13:22 UTC (rev 3195)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/Config.lb 2008-03-29 16:59:27 UTC (rev 3196)
@@ -20,3 +20,4 @@
config chip.h
driver cs5536.o
driver cs5536_ide.o
+driver cs5536_pirq.o
Added: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_pirq.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_pirq.c (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536_pirq.c 2008-03-29 16:59:27 UTC (rev 3196)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1)
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+ device_t pdev;
+
+ pdev = dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+
+ if (pdev) {
+ pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12
+ | pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));
+ }
+}
+#endif
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