[coreboot] MIPS Yamon replacement?

Robin Randhawa robin.randhawa at gmail.com
Thu Mar 27 15:32:08 CET 2008

Hi again.

On Thu, 2008-03-27 at 15:18 +0100, Carl-Daniel Hailfinger wrote:

> > Traditionally, the MIPS reset vector has been in what is known as the
> > KSEG1 window which is an uncached view of the lower 512MB of physical
> > memory and is accessible from physical address 0x1FC00000 onwards. I'll
> > be happy to provide any hints if you need them.
> >   
> Good. Now I just need to know how the ROM is mapped into that window.

I see. Sorry, I should've been more specific. Since the reset vector is
physical address 0x1FC00000 (which happens to be KSEG1 Addr 0xBFC00000 -
but that's getting too involved too soon), system designers ensure that
the Boot ROM begins at this address.

In the case of the Malta Evaluation board which MIPS advertises as the
evaluation board of choice, there is 4MB of NOR Flash which is mapped at
this location onwards.


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