[coreboot] Fwd: MIPS Yamon replacement?
djstunks at gmail.com
Thu Mar 27 14:45:10 CET 2008
---------- Forwarded message ----------
From: Jake Peavy <djstunks at gmail.com>
Date: Wed, Mar 26, 2008 at 9:19 PM
Subject: Re: [coreboot] MIPS Yamon replacement?
To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Forgot the list...
On 3/26/08, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> On 26.03.2008 21:05, Jake Peavy wrote:
> > Has anyone looked at porting Coreboot onto MIPS architecture? Can it be
> > used as a Yamon replacement?
> Nobody has looked into it yet, but we welcome all contributions to
> Coreboot, especially for non-x86 architectures. Please note, though,
> that the x86 arch (main support area for Coreboot) traditionally has
> extremely crappy firmware/BIOS compared to any other architecture. I
> have to admit that I just started to read up on Yamon and it roughly
> seems to do what we would achieve with a combination of Coreboot and a
> payload like OpenFirmware.
> Coreboot is designed to make lowlevel init fast and easy with clean and
> well-structured code, supporting diverse payloads. Target settings
> (northbridge, southbridge, SuperI/O) are compiled in except for the
> usual bus probing stuff. A Coreboot MIPS target could do it all
> differently, though. Unfortunately linux-mip.org is down and I could not
> find out whether Yamon really tries to support all available hardware
> with one binary. That would be impossible in the x86 world due to
> inability to probe certain stuff and due to size constraints.
> If you decide to look into Coreboot MIPS support, please don't study
> coreboot v2. The coreboot v3 architecture is a lot cleaner because we
> learned a lot with previous generations, the code is nicer and we even
> have a design document which is reasonably accurate. Of course, if the
> MIPS angle shows considerable problems with the current Coreboot v3
> design, we'd be happy to hear about it to improve the design.
> By the way, it would be nice to know how execution starts on MIPS (top
> or bottom of address space). I have a patch which adds handling for
> bottom-booting architectures to v3, but so far we have seen no use case.
I'd be interested in trying to help with this effort. It would be certainly
be a learning experience for me.
If Coreboot has been ported to PPC it might be very similar. Both PPC and
MIPS architectures are RISC based, but maybe that's where the similarities
Based on http://www.mips.com/media/files/MD00103-2B-4KE-SUM-02.04.pdfsection
6.1.5, MIPS execution begins at 0x1FC00000. At least on the MIPS32 core I
You mentioned payload, is this typically the S1 (MBR) code in x86 arch?
If you think a weakness can be turned into a strength, I hate to tell you
this, but that's another weakness.
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