[coreboot] Code flow from reset vector

Viswesh S viswesh_vichu at yahoo.com
Wed Mar 26 06:05:58 CET 2008


I understand the procedure in which internally how the CS register ( Segment selector and base address part) make sure that we point to the address 0xFFFFFFF0.

But my doubts are in this part.

1) We will be flashing the coreboot.rom into the BIOS flash, right ?

2) If we objdump coreboot.rom, dump all the sections, we dont see the reset vector part and also the address 0xFFFFFFF0.This could be because these sections are stripped off.Is it because of that ?

4) If they are stripped off, then when I flash the coreboot.rom, what do I flash into the address 0xFFFFFFF0, as the coreboot.rom doesnt even contain the data(opcodes ) to write in that location.

Am I missing anything.


ps:- I am trying to correlate my experience in embedded firmware exp, where the files we were flashing had absolute addresses and we could objdump the flash file to understand the code at each location.

Message: 5
Date: Wed, 26 Mar 2008 00:40:21 +0100
From: Peter Stuge <peter at stuge.se>
Subject: Re: [coreboot] Code flow from reset vector
To: coreboot at coreboot.org
Message-ID: <20080325234021.15330.qmail at stuge.se>
Content-Type: text/plain; charset=us-ascii

On Tue, Mar 25, 2008 at 12:02:15PM -0700, Viswesh S wrote:
> I understand the coreboot.rom is the BIOS code, which comes inside
> the address mapped in real mode.( 0xA0000 - 0x100000).

Mh, not only.

> If that is the case, then how do we write into the address
> 0xFFFFFFF0, while we flash the BIOS.

386 and up power up with CS set specially so that it "points" at
physical address 0xffff0000. Similar to the flat real mode idea.

A far/long jump changes CS into plain real mode so a far jump is
pretty common early in the boot process.



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