[coreboot] [PATCH] flashrom: Prepare for ICH7/ICH8 SPI support

[Uwe Hermann]

On Fri, Mar 14, 2008 at 04:12:58PM +0100, Carl-Daniel Hailfinger wrote:
> > That's better:
> >
> > # ./flashrom 
> > Calibrating delay loop... OK.
> > No coreboot table found.

> > Found chipset "Intel ICH8M", enabling flash write... Root Complex Base
> > Address Register = 0xfed18000
> > GCS address = 0xfed1b410
> > GCS = 0x60
> > SPIBAR = 0xfed1b020
> > SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock
> > Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8

Please make this additional debug output only appear when -V is used,
too much information casual users shouldn't have to see.


Uwe.
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