[coreboot] [PATCH] flashrom: Prepare for ICH7/ICH8 SPI support

[Ward Vandewege]

On Fri, Mar 14, 2008 at 03:36:47PM +0100, Carl-Daniel Hailfinger wrote:
> On 14.03.2008 15:23, Ward Vandewege wrote:
> > On Fri, Mar 14, 2008 at 02:52:25PM +0100, Carl-Daniel Hailfinger wrote:
> >   
> >> Testers wanted for all ICH versions!
> >>
> >>
> >> Prepare for ICH7/ICH8 SPI support by adding some debugging for all
> >> ICH* chipsets. Functionality (except printing) should be unchanged.
> >>     
> >
> > My laptop (Dell 1420N) has ICH8:
> >
> > # lspci -nn
> > 00:1f.0 ISA bridge [0601]: Intel Corporation 82801HEM (ICH8M) LPC Interface
> > Controller [8086:2815] (rev 02)
> >   
> 
> Thanks. Please try this new patch:

That's better:

# ./flashrom 
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH8M", enabling flash write... Root Complex Base
Address Register = 0xfed18000
GCS address = 0xfed1b410
GCS = 0x60
SPIBAR = 0xfed1b020
SPI Read Configuration: prefetching enabled, caching enabled, BIOS Lock
Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8
OK.
WARNING: size: 0 -> 4096 (page size)
WARNING: size: 0 -> 4096 (page size)
WARNING: size: 0 -> 4096 (page size)
WARNING: size: 0 -> 4096 (page size)
WARNING: size: 0 -> 4096 (page size)
No EEPROM/flash device found.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator