[coreboot] RCA RM4100 Build Tutorial

joe at smittys.pointclark.net joe at smittys.pointclark.net
Thu Mar 13 00:18:47 CET 2008

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> On Wed, Mar 12, 2008 at 10:24:05AM -0400, joe at smittys.pointclark.net wrote:
>>>  - Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
>>>    done for most Intel chipsets yet (?) Also, you can run x86info
>>>    or cpuinfo for more info, I think.
>> CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000
>> 00000000 00000000 00000000 00000000
>> CPU: L1 I cache: 16K, L1 D cache: 16K
>> CPU: L2 cache: 256K
> Hm, interesting. I wonder how this can work. Or maybe the kernel just
> "knows" that this CPU should have 256KB cache, but didn't actually check
> whether it's enabled? Or, well, maybe it's on by default and cannot be
> disabled at all on this CPU? Need to check some datasheets.
> Various Pentium II/III CPUs I tried on 440BX boards did not have their
> L2 cache initialized when I last checked, so I'm surprised this seems
> to work here...
Really? It seems to work fine on this board, have you tried any socket  
370's? Maybe it is just an issue with slot 1's?
>>> Btw, can you post a full boot log (coreboot + Linux) here for reference?
>> Do you want me to send it to the list, or post it on the wiki??
> To the list, just attach it to your next mail. You can then link to the
> list archive in the wiki then, if you want.
Will do as soon as I get a chance. So I added a hardware section with  
two pics, does that look ok?

Thanks - Joe

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