[coreboot] RCA RM4100 Build Tutorial

joe at smittys.pointclark.net joe at smittys.pointclark.net
Wed Mar 12 15:24:05 CET 2008

Quoting Uwe Hermann <uwe at hermann-uwe.de>:

> Hi,
> On Mon, Mar 10, 2008 at 07:41:28PM -0400, joe at smittys.pointclark.net wrote:
>> I added a Build Tutorial to the wiki:
>> http://www.coreboot.org/RCA_RM4100_Build_Tutorial
>> and linked it to the Supported Motherboards page.
> Great, thanks!
> I've done some cleanups on the page (small cosmetic fixes mostly). Some
> more comments on the contents:
>  - It would be nice if you could add one or two photos from the board.
Ok, I can do that.
>  - Also, please add a license tag to all your wiki pages and wiki
>    images. You can use {{PD-self}} or {{CC-by-sa-3.0}} etc. See for
>    example http://www.coreboot.org/ASUS_A8V-E_Deluxe_Build_Tutorial.
Ok, I can do that.
>  - Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
>    done for most Intel chipsets yet (?) Also, you can run x86info
>    or cpuinfo for more info, I think.
CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000  
00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After all inits, caps: 0383f1ff 00000000 00000000 00000040  
00000000 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Compat vDSO mapped to ffffe000.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
Freeing SMP alternatives: 14k freed
CPU0: Intel Mobile Intel(R) Celeron(TM) CPU          733MHz stepping 04

[root at localhost ~]# cat /proc/cpuinfo
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 11
model name	: Mobile Intel(R) Celeron(TM) CPU          733MHz
stepping	: 4
cpu MHz		: 733.160
cache size	: 256 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 mtrr pge mca cmov pat  
pse36 mmx fxsr sse up
bogomips	: 1467.20
clflush size	: 32
>  - How did you test the CDROM drive? Mounting something in Linux or
>    booting from CDROM? If the latter, how (which FILO options etc)?
Mounting a disk in Linux
>  - Does the modem really work and how was that tested? Does it need
>    special support in coreboot?
It is detected by the kernel ok, but I have not used it yet.
>  - Is there really an onboard-CF slot on the board? Or did you test
>    using an Cf-to-IDE adapter? Or both?
Yes there is an onboard CF slot. It is connected to the primary IDE  
controller. I did use a CF-to-IDE adapter, and that works fine.
>  - How was IR tested? Which Linux tools? Any coreboot/superio changes
>    required?
The IR is for the wireless keyboard, connected to COM2, as long as  
COM2 is enabled it works fine. I have not tested it with lirc and a  
remote yet.
>  - You marked 'PC Speaker' as N/A. Why? Try 'modprobe pcspkr' and then
>    do some beeping, e.g. using the tool 'beep' (apt-get install beep).
>    It should work, usually.
Even if there is no PC Speaker onboard? Would the beeping happen on  
the audio out?
> As for Wake-on-LAN, it can usually be implemented either fully in
> hardware or in the BIOS/firmware. If the latter you probably need some
> extra code in coreboot. If it's implemented in hardware it will probably
> work out of the box.
I agree but I have not tested it yet. It is enabled in the nics eeprom
>> I am going to send some users from my website to try it out. Some of
>> the info may be redundent but it is meant for a coreboot newby?
>> Does it look like newby material?
> It's fine, IMO, users should be able to follow the instructions.
> Btw, can you post a full boot log (coreboot + Linux) here for reference?
Do you want me to send it to the list, or post it on the wiki??

Thanks - Joe

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