[coreboot] PIC, APIC, XAPIC and XIOAPIC
segher at kernel.crashing.org
Tue Mar 4 21:10:19 CET 2008
> In LB stage, only PIC mode is applied, isn't it? However, I remember
> some people of LB community told me there was no ISR except the debug
> ISR during LB. So does this mean it totally unnecessary to setup PIC
> via C00h/C001h IO port in LB?
You need to set up the legacy PIC really early, since it doesn't
itself to any sane settings at bootup.
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