[coreboot] PIC, APIC, XAPIC and XIOAPIC

Feng, Libo Libo.Feng at amd.com
Tue Mar 4 11:08:02 CET 2008

Hi, all,

I am a little confused by PIC, APIC, XAPIC and XIOAPIC.

In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB?

APIC is setup only after OS runs and gets the interrupt routing from MPTable or ACPI table, is it correct? Then, what difference between APIC and XAPIC? Some documents say APIC has MMIO space registers at FEC00000h while XAPIC has PCI configuration space registers. But some documents seems to refer the same controller by APIC and XAPIC.

And XAPIC and XIOAPIC are the same things, aren’t they?

Please help me out, I am completely confused by these terms.

Best Regards

丰立波 Feng Libo @ AMD  Ext: 20906
Mobile Phone: 13683249071
Office Phone: 0086-010-62801406

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