[coreboot] Firmware hub flash addressing [off-topic]
r&d2 at dave-tech.it
Tue Jun 17 16:30:32 CEST 2008
> Sorry for posting a message that is a little bit off-topic.
> I'm working with a SST 8 Mbit Firmware Hub SST49LF008A flash connected
> to Geode LX LPC bus.
> I need to understand where flash registers are mapped in case the flash
> ID is set to 1 (this flash is not the boot flash that has ID=0).
> The datasheet just says about identification registers (same thing
> applies for other registers too):
> JEDEC ID Registers
> The JEDEC ID registers for the boot device appear at
> FFBC0000H and FFBC0001H in the 4 GByte system
> memory map, and will appear ***elsewhere*** if the device is not
> the boot device.
> Anybody can tell me what does "elsewhere" stand for in this sentence?
Some news ...
If I understand correctly, "elsewhere" is not defined by LPC/FirmwareHub
standard but it depends on LPC controller (that's why it is not
specified in flash datasheet). On GeodeLX/CS5536, when reading location
at 0xFFBC0000, CS5536 generates a Firmware Hub Memory Read cycle with
IDSEL=0 (I verified this with a logic analyzer connected to LPC bus). I
tried to access different locations but I was not able to make CS5536 to
generate read cycles with IDSEL different from 0. So I don't understand
how the physical addresses are related to the IDSEL that is sent on the
LPC bus by CS5536. Anybody can help?
DAVE Electronics System House - R&D Department
email: r&d2 at dave-tech.it
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