[coreboot] ram init help on the i82830

Joseph Smith joe at settoplinux.org
Wed Jun 4 04:59:41 CEST 2008


Good News!!!
I think I got it working :-)
I am running memtest86 right now and if all goes well I build it again with
filo and test it. 

First I tried with initializing each dimm socket. I booted to memtest and
it kept erroring out at 256mb. Because this is a double sidded 512MB
so-dimm, I figured out that each side of each dimm needs to be initialized.
So I came up with this:


	for (i = 0; i < MAX_DIMM_SIDES; i++) {
		dimm_end = pci_read_config8(ctrl->d0, DRB + i);
		if (dimm_end > dimm_start) {
			PRINT_DEBUG("    Sending RAM command 0x");
			PRINT_DEBUG_HEX32(reg32);
			PRINT_DEBUG(" to 0x");
			PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset);
			PRINT_DEBUG("\r\n");
			read32((dimm_start * 32 * 1024 * 1024) + addr_offset);
		}
		/* Set the start of the next DIMM. */
		dimm_start = dimm_end;
	}

It seems to work good so far, hopefully I will be submitting a patch soon.
Output from bootlog:

coreboot-2.0.0_IP1000 Tue Jun  3 21:56:32 EDT 2008 starting...
Setting initial registers....
Initial registers have been set.
Found DIMM in slot 00
DIMM is 0x0100 on side 1
DIMM is 0x0100 on side 2
DRB 0x60 has been set to 0x08
DRB1 0x61 has been set to 0x10
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x12
DRB3 0x63 has been set to 0x12
Found DIMM in slot 00, setting DRA...
DRA 0x70 has been set to 0x22
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
RAM Enable 1: Apply NOP
    Sending RAM command 0x00000010 to 0x00000000
    Sending RAM command 0x00000010 to 0x10000000
    Sending RAM command 0x00000010 to 0x20000000
RAM Enable 2: Precharge all
    Sending RAM command 0x00000020 to 0x00000000
    Sending RAM command 0x00000020 to 0x10000000
    Sending RAM command 0x00000020 to 0x20000000
RAM Enable 3: CBR
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
    Sending RAM command 0x00000060 to 0x00000000
    Sending RAM command 0x00000060 to 0x10000000
    Sending RAM command 0x00000060 to 0x20000000
RAM Enable 4: Mode register set
    Sending RAM command 0x00000030 to 0x000001d0
    Sending RAM command 0x00000030 to 0x100001d0
    Sending RAM command 0x00000030 to 0x200001d0
RAM Enable 5: Normal operation
    Sending RAM command 0x00000070 to 0x00000000
    Sending RAM command 0x00000070 to 0x10000000
    Sending RAM command 0x00000070 to 0x20000000
RAM Enable 6: Enable Refresh and IC

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org





More information about the coreboot mailing list