[coreboot] patch: clean up cx5536 power handling, get power working on usb port 3 on dbe62

[ron minnich]

On Tue, Jun 3, 2008 at 7:44 AM, Jordan Crouse <jordan.crouse at amd.com> wrote:

>> +             /* power control. This is bit USB_PWR_EN2 in the UUCO.
>> +              * From Jordan: The kernel never sees a header for
>> +              * this device.  It used to provide a OS visible
>> +              * device, but that was defeatured.  There are still
>> +              * some registers in the block that are useful for the
>> +              * firmware to setup, but nothing that a kernel level
>> +              * driver would need to consume.
>> +              *
>> +              * That said, VSA _does_ provide the header under
>> +              * device ID PCI_DEVICE_ID_AMD_CS5536_OTG, but it is
>> +              * hidden when 0xDEADBEEF is written to config space
>> +              * register 0x7C
>> +              * (southbridge/amd/cs5536/cs5536.c:492).
>> +              *
>> +              * If you need to write the port power settings you
>> +              * can find the resource in the PCI config space and
>> +              * write to it as usual, just make sure that you do it
>> +              * before the block gets DEADBEEFed.
>> +              */
>
> Please get rid of this - you don't need 20 lines of comment to explain
> three lines of code.
>

I want that comment somewhere. This stuff is obvious to knowledgeable
amd guys but not as obvious to those of us out here.

thanks

ron