[coreboot] msrtool

Peter Stuge peter at stuge.se
Sat Jul 12 21:56:43 CEST 2008


On Sat, Jul 12, 2008 at 09:02:36AM -0700, ron minnich wrote:
> Thanks for the decode!

Today's lesson: Don't trust my decodes right now.


> suggestion for all of us. Every time we decode this stuff, we
> *write a program* -- perl, C, who cares -- that does it for us.

Yeah. I did that. The diff output from your coreboot value vs. the
reference value is attached. As you can see I shifted some bits wrong
when doing the decode manually. I need some practice I guess.


> And, coreboot will have another cool property -- a huge suite of
> programs for figuring these settings out.

Yes, definately. I still want to fix up msrtool a little more but
will send very soon.


//Peter
-------------- next part --------------
--- coreboot.dec	2008-07-12 21:48:52.000000000 +0200
+++ unterm.dec	2008-07-12 21:49:16.000000000 +0200
@@ -1,10 +1,10 @@
-GLCP_DELAY_CONTROLS 0x4c00000f = 0x83f100aa56960344
+GLCP_DELAY_CONTROLS 0x4c00000f = 0xf2f100ff56960004
    63 EN Enable = 1: Use value in bits [62:0]
-   62 B_DQ Buffer Control for DQ DQS DQM TLA drive = 0: Quarter power
-   61 B_CMD Buffer Control for RAS CAS CKE CS WE drive = 0: Quarter power
-   60 B_MA Buffer Control for MA BA drive = 0: Quarter power
+   62 B_DQ Buffer Control for DQ DQS DQM TLA drive = 1: Half power
+   61 B_CMD Buffer Control for RAS CAS CKE CS WE drive = 1: Half power
+   60 B_MA Buffer Control for MA BA drive = 1: Half power
    59 SDCLK_SET SDCLK Setup = 0: Full SDCLK setup
-58:56 DDR_RLE DDR read latch enable position = 3
+58:56 DDR_RLE DDR read latch enable position = 2
    55 SDCLK_DIS SDCLK disable [1,3,5] = 1: SDCLK[4,2,0] output only
 54:52 TLA1_OA TLA hint pin output adjust = 7
 51:50 D_TLA1 Output delay for TLA1 = 0
@@ -13,10 +13,10 @@
 45:44 D_DQ_O Output delay for DQ DQM - odd byte lanes = 0
 43:42 [Reserved] = 0x0 0
 41:40 D_SDCLK Output delay for SDCLK = 0
-39:38 D_CMD_O Output delay for CKE CS RAS CAS WE - odd bits = 2
-37:36 D_CMD_E Output delay for CKE CS RAS CAS WE - even bits = 2
-35:34 D_MA_O Output delay for BA MA - odd bits = 2
-33:32 D_MA_E Output delay for BA MA - even bits = 2
+39:38 D_CMD_O Output delay for CKE CS RAS CAS WE - odd bits = 3
+37:36 D_CMD_E Output delay for CKE CS RAS CAS WE - even bits = 3
+35:34 D_MA_O Output delay for BA MA - odd bits = 3
+33:32 D_MA_E Output delay for BA MA - even bits = 3
 31:30 D_PCI_O Output delay for pci_ad IRQ13 SUSPA# INTA# - odd bits = 1
 29:28 D_PCI_E Output delay for pci_ad IRQ13 SUSPA# INTA# - even bits = 1
 27:26 D_DOTCLK Output delay for DOTCLK = 1
@@ -28,6 +28,6 @@
 15:14 D_VIPCLK Input delay for VIPCLK = 0
    13 H_SDCLK Half SDCLK hold select (for cmd addr) = 0: Full SDCLK setup
 12:11 PLL_FD_DEL PLL Feedback Delay = 0: No feedback delay
- 10:6 [Reserved] = 0x0d 13
+ 10:6 [Reserved] = 0x00 0
     5 DLL_OV DLL Override (to DLL) = 0
   4:0 DLL_OVS/RSDA DLL Override Setting or Read Strobe Delay Adjust = 4


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