[coreboot] [PATCH] (resend2) fix the flashrom problem on m57sli boards with SPI flash

Ward Vandewege ward at gnu.org
Thu Jan 31 03:13:19 CET 2008


On Thu, Jan 31, 2008 at 03:01:51AM +0100, Florentin Demetrescu wrote:
>  This patch fixes the decoding of the IO address range 0x0820->0x0827 into the
> LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
> interface of the IT8716 SIO chip.
>  Changes :
>   1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
> functions of a PNP device can have more than 12 resources (ex the GPIO function
> of IT8716f), in which case one could have an "array overflow" inside the device
> structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
> device init time..)
>   2) - define resource masks for the GPIO function in
> src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
> ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
> 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
> GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
> by the init code
>   3) - enable the flash SPI interface into
> src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
> into the GPIO function). I know that this is problematic because not all m57sli
> boards are SPI, but .. do anyone have a better idea how to handle this?..
> 
>  Signed-off-by: Florentin Demetrescu <echelon at free.fr>
> 
>  Patch file attached.

Great work! I can test this on Friday.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator




More information about the coreboot mailing list