[coreboot] PATCH: Add Spansion S25FL016A to flashrom

Peter Stuge peter at stuge.se
Fri Jan 25 02:11:40 CET 2008

On Thu, Jan 24, 2008 at 04:57:35PM +0100, Carl-Daniel Hailfinger wrote:
> > Then I wrote rand.bin which is 2MB of /dev/random. This
> > consistently reads back as something quite different
> This looks like the chip was not erased between writing
> 4*coreboot.rom and the random image.

You mean I have to erase? I forgot.

I'm thinking maybe -w should erase by default and that
another option (-W?) writes without erase. Thoughts?
I can save this idea for the ultimate larflash tool though.

> Can you verify the chip is indeed blank after erase, and then flash
> the random image again?

Yep, that works.

> > +	 probe_spi,	generic_spi_chip_erase_c7,	over512k_spi_chip_write, over512k_spi_chip_read},
> You can use generic_spi_* instead of over512k_spi_*.

Thanks, I was running with generic_, then I changed the code but
never rebuilt, read up on the thread and then forgot I had changed
the code before the svn diff.

Revised patch attached. Not the best performance, but it works.

m57sli tmp # time flashrom -m gigabyte:m57sli -w 2m.bin   
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial
flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
S25FL016A found at physical address 0xffe00000.
Flash part is S25FL016A (2048 KB).

real    10m10.446s
user    10m10.260s
sys     0m0.180s
m57sli tmp # 

-------------- next part --------------
Add ids and chip entry for Spansion S25FL016A to flashrom, tested, working.

Signed-off-by: Peter Stuge <peter at stuge.se>

Index: util/flashrom/flash.h
--- util/flashrom/flash.h	(revision 3073)
+++ util/flashrom/flash.h	(working copy)
@@ -166,6 +166,14 @@
 #define SHARP_LHF00L04		0xCF
+ * Spansion was previously a joint venture of AMD and Fujitsu.
+ * S25 chips are SPI. The first device ID byte is memory type and
+ * the second device ID byte is memory capacity.
+ */
+#define SPANSION_ID		0x01	/* Spansion */
+#define SPANSION_S25FL016A	0x0214
  * SST25 chips are SPI, first byte of device ID is memory type, second
  * byte of device ID is related to log(bitsize) at least for some chips.
Index: util/flashrom/flashchips.c
--- util/flashrom/flashchips.c	(revision 3073)
+++ util/flashrom/flashchips.c	(working copy)
@@ -56,6 +56,8 @@
 	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write, generic_spi_chip_read},
 	{"MX25L3205",	MX_ID,		MX_25L3205,	4096, 256,
 	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write, generic_spi_chip_read},
+	{"S25FL016A",	SPANSION_ID,	SPANSION_S25FL016A,	2048, 256,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write, generic_spi_chip_read},
 	{"SST25VF040B",	SST_ID,		SST_25VF040B,	512,	256,
 	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write, generic_spi_chip_read},
 	{"SST25VF016B",	SST_ID,		SST_25VF016B,	2048,	256,

More information about the coreboot mailing list