[coreboot] SST25VF016B (2MB) flash on m57sli (IT8716F).
ronald at zonnet.nl
Mon Jan 21 00:47:10 CET 2008
On Mon, 2008-01-21 at 00:24 +0100, Ronald Hoogenboom wrote:
> (LPC is the only datapath to the SB and CPU, so it has to!). We could
> optimize by omitting the wait for SPI ready when there is no data to be
> read, eg. readcnt==0. I'll have a look at what can be gained by that.
Omitting it saves 10 seconds with the unconditional 10us delay, reducing
to 40~45 secs. So I think it is worth putting it in. With the
conditional delay, it is not so easily measurable, because of the
natural variance much larger than 10 us...
Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 620 bytes
Desc: not available
More information about the coreboot