[coreboot] SST25VF016B (2MB) flash on m57sli (IT8716F).

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Jan 18 15:49:23 CET 2008

On 18.01.2008 08:17, ron minnich wrote:
> OK, SiS sent me this nice board with some 2 MB flash parts and I have
> not gotten much past step 1, "Program the flash", as it is a 2 MB
> flash. I had no idea what a mess the superio/flash interface was going
> to be.
> So, Ronald, I am most interested in your patch, hope it is ready soon!

I think one or two more iterations and we should be ready to go.

> And, well, seems we have a problem with 2 MB parts. Ouch. I guess what
> I will do for now is use 512KB of the 2 MB part (i.e. program it with
> 4 512KB images).

For now. We could certainly enable ROM shadowing in RAM if we can make
some RAM appear directly below 4 GB.

> I hate to say this, and I agree with the desire to remain clean in v3,
> but we may have to find a way to deal with this mess. I hope not.  It
> is hard to believe how brain-dead PC hardware can be, given that the
> same mistakes and lessons are learned (and forgotten) over and over
> again. Too bad.

I have a mad scheme which would work for v3 without downsides (except
for the fact that the boot block and initram have to be in the upper 512
kB, but that's the case anyway even without my scheme).
Basically, we create a flat LAR-in-LAR structure. Before you start to
barf, listen:
Instead of storing real flash size at the top of ROM, we store a virtual
size which corresponds to the start of the first LAR member in the top
512 kB block. This virtual size is what all LAR parsing uses until CAR
has been disabled. Then we shadow the entire ROM somewhere in RAM and
further accesses to the ROM will be directed there, including all LAR

> Anyway I am ready to test the patch tomorrow morning, I have a 1/2
> vacation day and intend to put it to good use ...

Can you test the modified variant I posted as a reply to Ronald? It
should work as well and fit a little better into flashrom structure.


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