[coreboot] AMD Family 0Fh CAR and L1 cache tags

[Marc Jones]

Carl-Daniel Hailfinger wrote:

> Errors = 0;
> channel = 0;
> while( (channel<2) && (!Errors)) {
> 	print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); 
> 	for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) {
> 		unsigned err;
> 		SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay);
> 		print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); 
> 		err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo);
> 		print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); 
> 		if(err == 0) break;
> -------------> Now we set "Errors"
> 		Errors |= err;
> 	}
> 	print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); 
> 	if(DQSWrDelay < 48) {
> -------------> Now we overwrite "Errors" in case the for loop above ever had err == 0.
> 		Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo);
> 		print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); 
> 	}
> 	channel++;
> 	if(!is_Width128){
> 		//FIXME: 64MuxMode??	
> 		channel++; // skip channel if 64-bit mode
> 	}
> }
> 
> 
> As I understand the logic of the snippet above, we look for a DQSWrDelay
> which does not give any errors with TrainReadDQS. Then we don't care
> about errors for other values of DQSWrDelay and use the current value of
> DQSWrDelay to run TrainWriteDQS.
> If TrainReadDQS failed for all values of DQSWrDelay, we return the
> bitwise OR of all error conditions we had for all values of DQSWrDelay.
> Does that really make sense?


Any bit set means fail. Caller checks !=0. I think it is fine. I guess 
it could be translated to a pass/fail. If there are no passing case the 
reason doesn't really matter. The real errors are reported in 
TrainDQSPos(). Does that answer your question?

Marc


-- 
Marc Jones
Senior Firmware Engineer
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mailto:Marc.Jones at amd.com
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