[LinuxBIOS] Intel refactoring and microcode updates

Uwe Hermann uwe at hermann-uwe.de
Fri Jan 11 09:27:18 CET 2008


On Tue, Jan 08, 2008 at 09:36:20PM -0500, Corey Osgood wrote:
> Both patches Signed-off-by: Corey Osgood <corey.osgood at gmail.com>

I checked that this doesn't break abuild, so far so good.

On which hardware has this been tested so far? I'm reluctant to commit
this without some broader testing on actual hardware. I'd say at least
some of the 440BX boards, i810, and others.

I can test some of the above soonish I hope, but someone with
server-grade boards should probably also do some tests (E7520 boards and
similar).


> Index: src/cpu/intel/microcode/2107-m406fbB4.inc
> ===================================================================
> --- src/cpu/intel/microcode/2107-m406fbB4.inc	(revision 0)
> +++ src/cpu/intel/microcode/2107-m406fbB4.inc	(revision 0)
> @@ -0,0 +1,266 @@
> +/**
> + *	Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000, 01, 02,
> + *	03, 04, 05, 06, 07.
> + *
> + *	These microcode updates are distributed for the sole purpose of 
> + *	installation in the BIOS or Operating System of computer systems
> + *	which include a Genuine Intel microprocessor sold or distributed
> + *	to or by you. You are not authorized to use this material for
> + *	any other purpose.
> +**/

Where exactly do these files come from (URL on intel.com?) We should
document this in either the files and/or the wiki.

I know about
http://www.urbanmyth.org/microcode/
http://people.debian.org/~cate/files/microcode/
is that the source?

There's also some stuff at
http://downloadcenter.intel.com/detail_desc.aspx?strstate=live&productid=528&dwnldid=14303&agr=n&lang=eng&prdmap=528
for example, which has a different license header, though:


/+++
/       Copyright (c) <1995-2008>, Intel Corporation.
/       All rights reserved.
/
/       Redistribution. Redistribution and use in binary form, without modification, are
/       permitted provided that the following conditions are met:
/               .Redistributions must reproduce the above copyright notice and the following
/       disclaimer in the documentation and/or other materials provided with the
/       distribution.
/               .Neither the name of Intel Corporation nor the names of its suppliers may be used
/       to endorse or promote products derived from this software without specific prior
/       written permission.
/               .No reverse engineering, decompilation, or disassembly of this software is
/       permitted.
/               ."Binary form" includes any format commonly used for electronic conveyance
/       which is a reversible, bit-exact translation of binary representation to ASCII or
/       ISO text, for example, "uuencode."
/
/       DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
/       HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
/       WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
/       WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
/       PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
/       OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
/       SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
/       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
/       LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
/       CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
/       STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/       ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
/       ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/
/       These microcode updates are distributed for the sole purpose of
/       installation in the BIOS or Operating System of computer systems
/       which include a Genuine Intel microprocessor sold or distributed
/       to or by you. You are not authorized to use this material for
/       any other purpose.
/---



> +/* Note: It is impossible to tell what Xeons are Socket 603 vs 604 from the info
> + * on Intel's website. Also, socket 603 CPUs work in 604 systems. Hence, 
> + * combined for good reasons. */
> +struct cpu_device_id cpu_table[] = {
> +	{ X86_VENDOR_INTEL, 0x0f0a },
> +	{ X86_VENDOR_INTEL, 0x0f11 },
> +	{ X86_VENDOR_INTEL, 0x0f12 },
> +	{ X86_VENDOR_INTEL, 0x0f22 },
> +	{ X86_VENDOR_INTEL, 0x0f24 },
> +	{ X86_VENDOR_INTEL, 0x0f25 },
> +	{ X86_VENDOR_INTEL, 0x0f26 },
> +	{ X86_VENDOR_INTEL, 0x0f27 },
> +	{ X86_VENDOR_INTEL, 0x0f29 },
> +	{ 0, 0 },
> +};
> +
> +struct chip_operations cpu_intel_socket_603_ops = {
> +	CHIP_NAME("Socket 603 CPU")

Shouldn't this be
        CHIP_NAME("Socket 603/604 CPU")
then?


> +/* Note: It is impossible to tell what Xeons are Socket 603 vs 604 from the info
> + * on Intel's website. Also, socket 603 CPUs work in 604 systems. Hence, 
> + * combined for good reasons. */
> +struct cpu_device_id cpu_table[] = {
> +	{ X86_VENDOR_INTEL, 0x0f22 },
> +	{ X86_VENDOR_INTEL, 0x0f24 },
> +	{ X86_VENDOR_INTEL, 0x0f25 },
> +	{ X86_VENDOR_INTEL, 0x0f26 },
> +	{ X86_VENDOR_INTEL, 0x0f27 },
> +	{ X86_VENDOR_INTEL, 0x0f29 },
> +	{ X86_VENDOR_INTEL, 0x0f34 },
> +	{ X86_VENDOR_INTEL, 0x0f41 },
> +	{ X86_VENDOR_INTEL, 0x0f43 },
> +	{ X86_VENDOR_INTEL, 0x0f48 },
> +	{ X86_VENDOR_INTEL, 0x0f49 },
> +	{ X86_VENDOR_INTEL, 0x0f4a },
> +	{ 0, 0 },
> +};
> +
> +struct chip_operations cpu_intel_socket_604_ops = {
> +	CHIP_NAME("Socket 604 CPU")

Same here?


> +/* Note: Intel does not explicitly state which CPUs are Socket M vs Socket P on their website, but there was a large overlap of the ones I could identify. Hence, this includes all Socket M and P CPUs, along with onboard Core, Core 2, and (Core/Core2 based) Celeron M CPUs, for convenience's sake */

Line is too long.


> +struct cpu_device_id cpu_table[] = {
> +	{ X86_VENDOR_INTEL, 0x06e8 },
> +	{ X86_VENDOR_INTEL, 0x06ec },
> +	{ X86_VENDOR_INTEL, 0x06f2 },
> +	{ X86_VENDOR_INTEL, 0x06f6 },
> +	{ X86_VENDOR_INTEL, 0x06fa },
> +	{ X86_VENDOR_INTEL, 0x06fb },
> +	{ X86_VENDOR_INTEL, 0x06fd },
> +	/* I don't know if we'll be able to see all 5 digits, so both are included */
> +	{ X86_VENDOR_INTEL, 0x10676 },
> +	{ X86_VENDOR_INTEL, 0x0676 },

Add a TODO here maybe, we should find out and fix it.


> +/* Slot 1 CPU IDs. Note that the same ID is sometimes used for Celeron,
> + * Pentium, and Xeon families, in various packages. This also includes
> + * Mobile Pentium II and Celeron families */
> +struct cpu_device_id cpu_table[] = {

Maybe
const struct cpu_device_id cpu_table[] = {

(same for most other files)


> +u32 microcode_updates[] = {

These arrays can be const too, I guess.


> Index: src/cpu/intel/intel_shared/intel_init.c
> ===================================================================
> --- src/cpu/intel/intel_shared/intel_init.c	(revision 0)
> +++ src/cpu/intel/intel_shared/intel_init.c	(revision 0)
> @@ -0,0 +1,53 @@
> +#include <console/console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <cpu/cpu.h>
> +#include <cpu/x86/mtrr.h>
> +#include <cpu/x86/msr.h>
> +#include <cpu/x86/lapic.h>
> +#include <cpu/intel/microcode.h>

> +#ifdef CONFIG_SMP
> +#if CONFIG_SMP

Why both?


> Index: src/cpu/intel/intel_generic/intel_generic.c
> ===================================================================
> --- src/cpu/intel/intel_generic/intel_generic.c	(revision 0)
> +++ src/cpu/intel/intel_generic/intel_generic.c	(revision 0)
> @@ -0,0 +1,85 @@
> +#define NO_MICROCODE_UPDATES
> +#include "../intel_shared/intel_init.c"
> +#include "chip.h"
> +
> +/* CPU IDs for all >=PPro x86 and x86_64 Intel CPUs, as of 12/30/2007, without 
> + * the microcode updates. Microcode updates should be done later, with recent 
> + * kernels this is done automatically, just put the latest microcode update file
> + * in /etc/firmware */
> +struct cpu_device_id cpu_table[] = {

> +/* TODO!!! */

What exactly?


> Index: src/mainboard/a-trend/atc-6220/Config.lb
> ===================================================================
> --- src/mainboard/a-trend/atc-6220/Config.lb	(revision 3036)
> +++ src/mainboard/a-trend/atc-6220/Config.lb	(working copy)
> @@ -82,7 +82,7 @@
>  
>  chip northbridge/intel/i440bx		# Northbridge
>    device apic_cluster 0 on		# APIC cluster
> -    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
> +    chip cpu/intel/slot_1		# CPU
>        device apic 0 on end		# APIC
>      end
>    end

Nice, thanks. This was on my TODO list, too.


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org




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