[coreboot] v3 smbus device structure

Marc Jones marc.jones at amd.com
Fri Feb 22 22:02:51 CET 2008

We need to discuss v3 smbus operations. Someone has done a lot of work 
to make smbus_ops.c and smbus.h. The code treats smbus as a bus, like 
the pci bus, with a device structure and all.

This approach seems nice and maybe the right way to do it, but it is 
somewhat overkill. I think that the complexity is one reason why the 
structure is in place in v2 but never used. Instead, simpler 
chipset/mainboard specific functions are used. The other reason is that 
the smbus is accessed in ROMCC/CAR code and not in the main coreboot bus 
enumeration code. My observation is that the SPD is the only device on 
smbus used by most mainboards in coreboot.

So, what do we want to do for v3? If we go with the bus/device structure 
every mainboard in v2 will need to have the smbus functions ported. 
Also, someone will have to figure out how to describe the smbus devices 
in the dts and the entire thing might need to use a simpler bus/device 
structure. Or, we can do as was done in v2 and leave it to the 
chipset/mainboard code.

Thoughts? Volunteers?

Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

More information about the coreboot mailing list