[coreboot] SST25VF016B (2MB) flash on m57sli (IT8716F).

Ward Vandewege ward at gnu.org
Wed Feb 20 05:34:54 CET 2008


Hi Ronald,

On Mon, Feb 18, 2008 at 10:45:23PM +0100, Ronald Hoogenboom wrote:
> Finally, now I know it's working (at least the part that I'm patching
> here...), here is the patch that uses PIO mode read from SPI rom with
> lzma decompression.
> 
> This patch allows direct out-of-SPI-flash boot of a Linux kernel. It
> circumvents the 512KB limitation in the IT8716f superio of memory
> mapping an SPI flash device by using a PIO method for reading the data.
> Limitation: no nrv2b support.

I've tested this on an m57sli-s4 (soic/spi revision) with a 2MB SPI chip, and
it boots. Great work!

> Not so nice: hardcoded 0x820 SPI-IO port.

Is that superio specific? Maybe some sort of lookup table based on the
superio in use would be a solution? At this point there would be just the one
line I presume.

> Signed-off-by: Ronald Hoogenboom <hoogenboom30 at zonnet.nl>

I won't pretend to understand everything, but I have a few comments, see
below.

> Index: src/southbridge/nvidia/mcp55/mcp55_lpc.c
> ===================================================================
> --- src/southbridge/nvidia/mcp55/mcp55_lpc.c	(revision 3103)
> +++ src/southbridge/nvidia/mcp55/mcp55_lpc.c	(working copy)
> @@ -243,7 +243,7 @@
>  static void mcp55_lpc_read_resources(device_t dev)
>  {
>  	struct resource *res;
> -	unsigned long index;
> +	//unsigned long index;

What's this change for? Unrelated to the rest of the patch? If it's general
cleanup, please do this in a separate patch.

<snip>

> Index: src/mainboard/gigabyte/m57sli/Options.lb
> ===================================================================
> --- src/mainboard/gigabyte/m57sli/Options.lb	(revision 3103)
> +++ src/mainboard/gigabyte/m57sli/Options.lb	(working copy)
> @@ -42,7 +42,7 @@
>  uses ROM_IMAGE_SIZE
>  uses ROM_SECTION_SIZE
>  uses ROM_SECTION_OFFSET
> -uses CONFIG_ROM_PAYLOAD
> +uses CONFIG_PIOROM_PAYLOAD
>  uses CONFIG_ROM_PAYLOAD_START
>  uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
>  uses CONFIG_COMPRESSED_PAYLOAD_LZMA
> @@ -80,6 +80,7 @@
>  uses OBJCOPY
>  uses CONFIG_CHIP_NAME
>  uses CONFIG_CONSOLE_VGA
> +uses CONFIG_VGA_ROM_RUN
>  uses CONFIG_USBDEBUG_DIRECT
>  uses CONFIG_PCI_ROM_RUN
>  uses HW_MEM_HOLE_SIZEK
> @@ -211,7 +212,8 @@
>  
>  #VGA Console
>  default CONFIG_CONSOLE_VGA=1
> -default CONFIG_PCI_ROM_RUN=1
> +default CONFIG_VGA_ROM_RUN=1
> +default CONFIG_PCI_ROM_RUN=0

Unrelated to the rest of the patch? I'm not sure I want this default to
change - it's nice to have any PCI roms run by default.

>  #default CONFIG_USBDEBUG_DIRECT=1
>  
> @@ -253,8 +255,8 @@
>  ##
>  default MAINBOARD_PART_NUMBER="m57sli"
>  default MAINBOARD_VENDOR="GIGABYTE"
> -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
> -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
> +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1458
> +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xe000

Also unrelated to the rest of the patch? This does not seem to have any
effect on my box. Also; the proprietary bios uses 0x1022; why are you
changing this?

This is great work; if you can respond to the comments above I think I can
ack this soon.

Thanks,
Ward.

-- 
Ward Vandewege <ward at fsf.org>
Free Software Foundation - Senior System Administrator




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