[coreboot] r596 - coreboot-v3/northbridge/amd/geodelx

[svn at coreboot.org]

Author: hailfinger
Date: 2008-02-13 23:51:03 +0100 (Wed, 13 Feb 2008)
New Revision: 596

Modified:
   coreboot-v3/northbridge/amd/geodelx/geodelx.c
   coreboot-v3/northbridge/amd/geodelx/raminit.c
Log:
Remove some remaining code inside #if 0.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Builds and run to filo.
Acked-by: Marc Jones <marc.jones at amd.com>


Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c	2008-02-13 22:47:58 UTC (rev 595)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c	2008-02-13 22:51:03 UTC (rev 596)
@@ -163,20 +163,6 @@
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
 	enable_shadow(dev);
-
-#if 0
-	/* Swiss cheese */
-	msr = rdmsr(MSR_GLIU0_SHADOW);
-
-	msr.hi |= 0x3;
-	msr.lo |= 0x30000;
-
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-	       MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-	       MSR_GLIU1_SHADOW, msr.hi, msr.lo);
-	/* TODO: Is the respective wrmsr() missing? */
-#endif
 }
 
 /**

Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-02-13 22:47:58 UTC (rev 595)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-02-13 22:51:03 UTC (rev 596)
@@ -216,15 +216,6 @@
 	if (spd_byte1 == 0xFF)
 		spd_byte1 = 0;
 
-	/* I don't think you need this check. */
-#if 0
-	if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0) {
-		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n");
-		post_code(POST_PLL_MEM_FAIL);
-		hlt();
-	}
-#endif
-
 	/* Use the slowest DIMM. */
 	if (spd_byte0 < spd_byte1)
 		spd_byte0 = spd_byte1;
@@ -580,13 +571,6 @@
 	msr.lo &= ~0xF0;
 	msr.lo |= 0x40;		/* Set refresh to 4 SDRAM clocks. */
 	wrmsr(MC_CF07_DATA, msr);
-
-	/* Memory Interleave: Set HOI here otherwise default is LOI. */
-#if 0
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.hi |= CF8F_UPPER_HOI_LOI_SET;
-	wrmsr(MC_CF8F_DATA, msr);
-#endif
 }
 
 /**